200 Ty J. Prosa and David J. Larson


Figure 8. Correlative tEBSD orientation maps (a, d, and c) and APT atom maps (b and e) from a group of alumina grains all collected from a single APT specimen (reprinted from (Chen et al., 2015) with permission).


properties that are intentionally deposited adjacent to each other. The material interfaces are both parallel and perpen- dicular to the substrate, may be conducting or insulating, with high- or low-evaporation fields, potentially with voided regions, and often all of these material types may be within a few nanometers of each other. Because of this complexity, it is difficult to predict the result of an APT analysis, whether the specimen will survive and how the evaporation field differences of the materials will limit reconstruction accuracy. Nevertheless, a number of successful analyses have been reported (for a recent review and further references see Larson et al., 2016), and the authors suspect many additional successes have been achieved but not made available in the literature because of the intellectual property value of those studies to the semiconductor industry. Before describing the various preparation strategies in


detail, a discussion of the potential tradeoffs inherent for these strategies applied to particular device types is warranted. The current state-of-the-art device technology is the 14-nm finFET and billions of these transistors are present in the newest mobile phones currently made by Samsung, Apple, and other manufacturers. The general structure is shown in Figure 9with the finFET generally consisting of multiple silicon fins along one direction, and a series of high-κ, multilayer metal gates making contact perpendicular to the fins.Eachof these 3D structures is surrounded by electrical insulators that are periodically interspersed with electrical contacts that typically contain tungsten wrapped with multiple layers of other contact material (not shown in the figure). For these small structures, it is certainly possible to include one complete repeating element within a specimen because they are so small; however, the presence of so many disparate materials and interfaces


Figure 9. General structure of a modern finFET. The character- istic dimension (fin width) can range from 10-22nm for scale (graphic based on 2014 Intel video by Mark Bohr, “14nm Transistor Explained –Following the Path of Moore’s Law”).


increases the chances for specimen failure as well as adds complexity to the reconstruction. A better approach for this smallest node technology, which is also applicable to much larger device nodes, is to decide in advance what aspect of the device is of interest and to focus the preparation and analysis strategy around this goal. Consider analysis of the fin region of the finFET, for


example. There are at least four different ways to capture the fin within an APT specimen and these are sketched in Figure 10 fromleft to right: top-down, backside, cross-section


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