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www.us-tech.com


May, 2018


Triangulating BGA Faults with Boundary Scan


By Ryan Jones, Senior Technical Marketing Engineer, Corelis, Inc.


defects after assembly, but some- times detection alone is not enough. Today’s fine-pitch ball grid array (BGA) devices, in particular, present real problems. There is often no physical or visible access to the de- vice pins, limiting diagnostic capabil- ity. Even when an open circuit is de- tected between two BGA devices, this data alone is not enough to deter- mine which device is actually at fault. Even X-ray inspection equip- ment cannot always provide conclu- sive visual evidence when such a de- fect is encountered.


V


Fault Detection with JTAG When it comes to structural


testing of printed circuit board (PCB) assemblies that include BGA devices, JTAG is a preferred test method since it is not reliant on physical ac- cess to each pin. Since BGA packag- ing does not offer direct physical ac- cess to external probes, this makes using external probe methods, such as in-circuit test (ICT) and flying probe testing, ineffective. In JTAG devices, the test circuit-


ry resides inside the chip itself and is controlled by the JTAG test access port (TAP) — a simple five-wire inter- face. Using this circuitry, boundary scan allows physical pins on the chip


JTAG testing can be used to identify faults between BGA boundary scan devices.


the expected pattern on correspon- ding pins. When the patterns match, it means that there is continuity be- tween the pins. If we expect continu- ity to exist between the two pins and the test patterns do not match, then there is likely a defect present. Even if JTAG tests can correctly identify the defect as an open circuit, they cannot isolate which device has the open pin, even if the driver and re- ceiver are swapped. Without know-


fault isolation. For example, if one BGA pin is open due to an assembly fault, a pin on the third JTAG-com- pliant BGA device would be able to confirm continuity to the good BGA pin. The remaining pin, which still cannot be confirmed for continuity, represents the faulty device. With this additional information, it is easy to identify the likely fault as an open solder ball and isolate repairs to just the faulty BGA device.


isual inspection and electrical testing can be highly success- ful at identifying board-level


to become JTAG test points. This is decisively different from external probes that physically access test points on the unit under test (UUT). During a JTAG test, one JTAG-


compliant BGA device drives test patterns on its pins, while a second JTAG-compliant BGA device verifies


ing exactly which device is causing the fault, repair work can turn into a 50/50 guess for technicians, resulting in unnecessary repairs.


Isolating and Diagnosing Faults Ideally, a third JTAG pin in the


circuit will be available to assist in Not all circuits will include


more than two JTAG pins and, even in cases of three or more pins, the ad- ditional pins might not offer JTAG control. In these cases, it is possible to externally attach a general-pur- pose IO (GPIO) pin from the JTAG controller to the circuit using a pas- sive component, test point, via, or the actual trace itself. If the driving BGA pin makes a successful connection, the GPIO pin will receive the expect- ed test pattern when JTAG test vec- tors are applied. If the driving BGA pin does not make a connection (open fault), the GPIO pin will not receive the expected test pattern when JTAG test vectors are applied, indicating a lack of continuity. This way, the fault can be pinpointed to a single pin.


JTAG Starter Kit Corelis offers a JTAG starter


kit, which is a toolset with every- thing required to isolate the problem when BGAs have an open fault. The kit includes a variety of tools and fea- tures to control and observe system signals of a boundary scan compati- ble UUT. The included USB 2.0 con- troller allows JTAG commands to be executed from any Windows-based PC and provides convenient GPIO circuitry that can be utilized as addi- tional measurement pins to help iso- late open failures between BGA pins.


Continued on page 46


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