February, 2017
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Page 73 JTAG Pushes Boundary Scan Envelope
Eindhoven, the Netherlands — JTAG Technologies is premiering several new hardware products for PCB testing and in-system device programming, and is also introducing its collaborative product with Altium — JTAG Maps. A large number of today’s electronic designs
contain JTAG/boundary scan components that prove to be valuable test resources during hardware debug, manufacturing test and even during depot repair. JTAG Maps is a simple extension to the Altium Designer suite that allows the user to thor- oughly assess the capabilities of the boundary scan resources in a design, before committing to layout.
JTAG Maps Until now, engineers could often spend hours
manually highlighting the boundary scan nets of a design to assess the fault coverage that boundary scan testing could bring to it. Today, the free JTAG Maps for Altium application extension does all of this and more, freeing up valuable time and allowing a more thorough DFT, as well as speeding product time-to-market. Boundary scan device models
(BSDLs) are integral to any JTAG/ boundary scan process, as they indi- cate precisely which pins can be con- trolled or observed by boundary scan. However, BSDL models are not always available in a timely manner. To overcome this painful problem, JTAG Maps for Altium includes an “assume scan covered” feature that enables a view of potential boundary scan coverage without a specific BSDL. This feature can also be used to highlight the differences in fault coverage between two equivalent parts, one with and one without built- in boundary scan. JTAG Maps for Altium will auto-
matically detect the scan chain path (or paths) with no limit on the number of paths, or TAPs, in the design. The nets associated with the TAPs will be highlighted separately from the “testable” nets, using different colors. While most users may only
want to use the quick coverage report that JTAG Maps can provide, it is also possible to import a more accu- rate picture. After exporting a JTAG Pro Vision project, the data can be
JTAG Maps for Altium Designer.
ture, multiple JT 5705/FXT tester cards can be mounted on purpose-built carriers equipped with ATE industry-standard pylon connectors, making
test system build simple. The company has also developed its CTPG-M
emulative test and programming technology, which is an automatic generator for testing con- nectivity between a core and all kinds of memory devices. The technology can emulate a micro- processor or the internal bus of an FPGA and refer to any memory devices with CTPG-M. JTAG’s new JTAG-powered PCB tester/pro-
grammer, the JT 57XX/RMI Combi-System is a mod- ular, base-level 1U rack-mount chassis assembly that can house up to four customer-specified mod- ules, offering various JTAG controllers, digital and
analog I/O, and other measurement features. Contact: JTAG Technologies, Inc., 111 N West
Street, Suite A, Easton, MD 21601 %410-770-4415 fax: 410-770-4774 E-mail:
info@jtag.com Web:
www.jtag.com r
See at IPC APEX, Booth 3435
JTAG 5705/FXT compact, multi-function JTAG tester.
sent to a JTAG Technologies office, approved application provider, or an approved JTAG representative for further analysis. A simple message file containing full fault-coverage information can then be read back into JTAG Maps for display and highlighting.
Latest JTAG Hardware The latest product on display by
JTAG is its “fixture embedded” test technology, the JT 5705/FXT multi- function JTAG tester built into one of the small linear series of cassette- based reconfigurable fixtures made by Everett Charles Technologies (ECT). The tester is a compact, single-
board test system that supports ana- log measurement and stimulus, fre- quency measurement, digital I/O, boundary scan testing, and in-system device programming. Within the fix-
See at APEX, Booth 1704 and at ATX West, Booth 4527
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