TECHNOLOGY UV LEDs
One option for increasing light extraction in these devices is to follow a widely adopted approach for boosting the brightness of blue LEDs. Forming these blue-emitting chips on micro- cone-shaped, patterned-sapphire has not only increased light extraction, but also enhanced crystal quality, leading to a substantial hike in luminous efficiency. However, care must be taken when attempting to replicate this type of approach with DUV LEDs, because AlN does not completely coalesce to form a smooth surface on conventional, micrometre-scale patterned sapphire. Why? Because the aluminium species have a low surface mobility.
Some research groups have suppressed crystal defects, both in AlN and in the upper epilayers, by turning to epitaxial lateral overgrowth techniques on either micro-striped patterned sapphire, or on templates formed by the growth of AlN on a flat sapphire substrate. AlN can then coalesce on unetched flat regions, leading to enhanced light output and external quantum efficiency for the DUV LEDs. However, this approach is not without its penalties. Due to the large space between the micro- patterns, coalescence thicknesses for AlN can be up to 10 µm, and this leads to far greater epitaxial time and cost.
From micro to nano To trim the coalescence thickness while maintaining a high output power for the DUV LED, our team at the Institute of Semiconductors at the Chinese Academy of Sciences has developed novel nano-patterned sapphire substrates. They form the foundation for nanoscale epitaxial layer overgrowth of an AlN template layer for DUV LEDs (see Figure 1).
Turning to these nano-patterned substrates slashes the coalescence thickness of the AlN film to just 3 µm. This is not at the expense of material quality − according to high- resolution X-ray diffraction and cross-sectional transmission electron microscope analysis of AlN and upper epilayers − and it enables the fabrication of LEDs with an impressive level of performance. Driven at 20 mA, a 282 nm LED formed on this foundation produces nearly twice the output power of an equivalent device formed on a conventional AlN-on-sapphire template.
Forming nano-patterned sapphire involves dip-coating and cleaning processes
We formed our patterned sapphire with a nanosphere lithography technique that involves wet-etching (see Figure 2). We begin by depositing a 200-nm-thick SiO2
film onto
2-inch (0001) sapphire by plasma-enhanced CVD. A positive photoresist is then spin-coated on this oxide, before a highly ordered self-assembled monolayer of polystyrene nanospheres is added via dip-coating. The wafer is then exposed to UV light using conventional photolithography, before the nanospheres are removed with deionised water and the photoresist developed to form nano-sized holes. Subsequent inductively
coupled plasma etching transfers this pattern to the SiO2 film, before the sapphire substrate is etched for 10 minutes in a mixture of H2
SO4 removed by HF.
This process creates a sapphire substrate that is patterned with concave triangular cones, which have dimensions defined by the anisotropic etching of the sapphire crystal (see Figure 3 for scanning electron microscopy images of pattern sapphire with periods of 900 nm and 600 nm).
Growth of our epistructure is undertaken with our homebuilt low-pressure MOCVD tool. It is fitted with trimethylaluminum, trimethylgallium and ammonia for providing aluminium, gallium and nitrogen sources, respectively.
Figure 1. The device structure of the DUV LED on flat sapphire substrate with a 1-µm-thick AlN template layer (a) delivers an inferior performance compared to that built on a nano-patterned sapphire substrate with a 4-µm-thick AlN template layer (b)
Starting with nano-patterned sapphire with a 900 nm period, we deposit a 25-nm low-temperature AlN buffer layer at 550 °C, before ramping the temperature to 1200 °C to grow a 4-µm AlN template. Growth of this layer occurs under continuous flow, with a relatively low V/III ratio of below 1000 and a low chamber pressure of 50 torr.
January / February 2014
www.compoundsemiconductor.net 51 and H3 PO4 solution and the SiO2 mask
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