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TECHNOLOGY VCSELs


Efforts by NCTU were followed by a flurry of results showing device improvements (see Figure 3 for details). In 2008 Nichia Corporation reported the first electrically injected lasing at room temperature, using a device based on a flip-chip geometry. By employing a vertical contact configuration and mounting a chip that features double-dielectric DBRs on a highly thermally conductive silicon substrate, the researchers addressed three issues: current crowding, low thermal conductivity of sapphire, and the challenges associated with III-nitride DBR growth. Thanks to these refinements, the VCSEL did not suffer from a hike in operating voltage that can occur with severe current crowding and lead to greater heat generation. Optical losses were minimal in the device, thanks to the high reflectivity of the DBR.


To form this chip, the researchers began by forming an epiwafer on c-plane sapphire with an active region comprising a two-period stack of interleaving 9 nm-thick quantum wells and 13 nm-thick barriers. Current injection


occurred through an 8 µm diameter, SiO2 aperture covered with 50 nm of ITO, plus metal electrodes that formed the p-side contact. Measurements revealed that the ITO had an optical loss of


0.5 percent near the lasing wavelength, so to minimize this, the team added an Nb2


O5 standing-wave null.


Final fabrication steps included deposition of an 11.5 period SiO2


/Nb2 O5


bottom DBR over a portion of the current injection area, the addition of a bonding metal to the top of the planarized structure, and flip-chip bonding to a silicon substrate, followed by sapphire removal via laser lift-off. Chemical- mechanical polishing thinned the n-side of the bonded epitaxial layers to 1.1 µm, before the team added an n-contact and a seven period SiO2


/Nb2 O5 top DBR.


The 414.4 nm VCSEL that resulted was capable of delivering continuous- wave emission at room temperature, had a threshold current of 7.0 mA and threshold current density of 13.9 kA cm-2


layer with a thickness of λ/8. This positioned the centre of the ITO at a


was linearly polarized, its orientation with respect to the crystal axes was unclear and probably random. That’s not surprising, given the cylindrical symmetry of the VCSEL cavity and relatively isotropic gain in the quantum well plane. Developers of this device also noted non- uniformity in the lasing spot across the current aperture. This might be due to inhomogeneities in cavity length, surface morphology, or active region quality.


By turning to dielectrics for both the mirrors, the researchers circumvented challenges associated with the growth of high-reflectivity, crack-free DBRs, and they also benefited from superior heat dissipation and current injection. But they paid a penalty for all of this: greater process complexity. Fabrication of a double-dielectric VCSEL involves bonding, laser lift-off and well-controlled thinning. Cavity-length control is also


tough, because it is difficult to polish a large-area substrate in a uniform manner to a sub-micron thickness.


Better foundations Following in the footsteps of developers of GaN-based edge-emitting lasers, Nichia’s researchers switched to free-standing GaN substrates. That move increased the room temperature, continuous-wave output power of their VCSELs by almost a factor of five to 0.62 mW. Improvement stemmed from slashing the defect density in the epitaxial layers by three orders of magnitude to several million per square centimetre.


The team attributed the higher output power of its VCSEL – which employed the same fabrication and device structure as its predecessor, with the exception of the substrate removal process – to a more uniform and complete filling of


,


and produced a peak output of 0.14 mW. Threshold voltage for the device was a relatively low 4.1 V – about half that of the VCSEL from NCTU – due, most likely, to vertical current injection.


Although the emission from this laser


Figure 2: GaN VCSEL structures that have been demonstrated. The top structure requires wafer bonding and removal of the substrate from the cavity using thinning or etching. The bottom structure utilizes a lattice-matched epitaxial bottom DBR and a dielectric top DBR


January / February 2014 www.compoundsemiconductor.net 47


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