TECHNOLOGY LOGIC


transistor’s channel – either electrons or holes, depending on the particular transistor − to travel far faster from the source to the drain. Today, increases in the charge carrier velocity in silicon often result from the application of very high levels of strain in the material, but the opportunities for further gains are now minimal, especially for n-type transistors.


What is possible is that the next revolution in the semiconductor industry will come from the introduction of compound semiconductors as channel materials. Electron and hole mobilities in silicon are just 1400 cm2 450 cm2


V-1 V-1 s-1 s-1 and , respectively, and far


higher values are promised by switching to carefully selected III-V and IV-IV compounds. For example, the electron mobility in InGaAs is in excess of 10,000 cm2


V-1 s-1 SiGe can hit 1900 cm2


, while hole mobility in V-1


s-1 . Using these


materials to form the p-type and n-type transistors for CMOS chips would allow the indium and germanium content in the channels to become a new scaling parameter, gradually increasing the carrier velocity for each new technology node and thus improving performance while lowering power consumption.


Researchers will have to answer many questions before it is possible to build


hybrid dual-channel CMOS circuits featuring very-large-scale integration (VLSI). They include: How do you get high-mobility channels on a silicon substrate with a good crystalline quality? How do you build nano-scaled devices based on III-Vs and SiGe that are compatible with VLSI? And how do you co-process both types of devices, given the fundamentally different thermal budgets and chemistries that they require?


A team at the IBM Zurich Research Laboratory in Switzerland has been focusing on finding answers to these questions for the last eight years.


January / February 2014 www.compoundsemiconductor.net 31


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