TECHNOLOGY LOGIC
Turbocharging channels with compounds
To maintain the improvements in efficiency that traditionally result from shrinking transistor dimensions, foundries will soon have to replace silicon channels with those based on higher mobility semiconductors. This move, a monumental upheaval for the silicon industry, could be easiest to implement by turning to engineered wafers with separate layers for the p-type and n-type transistors, argues Lukas Czornomaz from the Advanced Functional Materials Group at IBM Zurich.
FOUR DECADES of scaling CMOS technology has revolutionized our society. By making transistors ever smaller, faster, cooler, and cheaper, and being able to pack billions of them on the same chip, engineers have enabled the smartphone to become a commodity. This sleek, portable device has fundamentally changed the way we live: Now, wherever we are, we can be participating members of social networks and surfers of the web.
Performance of the smartphone will continue to increase, but it will not be easy to realise further gains in the computational capability of the chips that
lie at the heart of these devices. That’s because the microelectronic industry is facing some really serious challenges in shrinking dimensions beyond the 14 nm node.
Even getting as far as we have today has not been easy. For the last decade, pure geometrical scaling has failed to deliver the expected benefits in terms of performance and power consumption, and industry has gradually moved to innovation-driven scaling, bringing to market chips based on the likes of
strained silicon-on-insulator, high-κ/ metal gate technology and tri-gate devices. Now researchers everywhere
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www.compoundsemiconductor.net January / February 2014
are foreseeing that in the coming years, silicon – regardless of its form - will probably fail to meet the ultra-low power consumption targets imposed by the exploding demand of ‘Mobile- Everywhere’ applications.
The main lever for power scaling is the operating voltage of the chips. The target is to trim this from 0.8-0.9 V, which is where it stands today, down to 0.5 V. This cut in operating voltage must go hand-in-hand with a maintaining of the drive-current for the transistors, in order to ensure no reduction in performance. But realising this will not be easy. It will require the charge carriers in the
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