TECHNOLOGY LOGIC
Figure 4 (above). Cross-sectional TEM view of densely packed InGaAs devices on silicon substrates with gate lengths of only 24 nm
enviable starting point, this comes at the penalty of more challenging material processing. InGaAs and SiGe exhibit fundamentally different chemical natures, so processes that work fi ne with one material can cause etching of the other. To address this, the researchers modifi ed the fabrication fl ow for building InGaAs transistors on insulator, introducing new chemical cleans, passivation and etch- stop layers.
Thanks to all these developments, the team has have been able to demonstrate the fi rst construction of dense arrays of CMOS inverters built with 90 nm design rules on silicon substrates that feature high-mobility channel materials (see Figure 5b). Inverters are the simplest logic block, and an important step towards the building of more complex CMOS circuits. Thus, by showing an InGaAs/SiGe inverter operating down to 0.2 V (see Figure 5c), the concept of using high mobility materials for CMOS has been validated. What’s more, the door has been opened to further developments that could ultimately enable an up-scaling of the technology for high-volume manufacturing.
Clearly, the next steps are to build more complex CMOS circuits such as ring-oscillators and SRAM cells (a very common memory cell featuring six transistors). Armed with these circuits, the team will be able to assess the speed, performance and maturity of this advanced CMOS technology. However, the key test for this hybrid circuit will be to scale its dimensions to that of a state-of-the-art silicon chip and see how it compares. If it performs well, introduction in the foundries will then hinge on
Figure 5. (a) Schematic process fl ow for the fabrication on hybrid InGaAs/SiGe CMOS circuits based on high-mobility dual-channel substrates. (b) Top-view SEM image on a dense CMOS inverter chain fabricated with 90nm design rules. (c) Hybrid CMOS inverter output characteristic showing a working circuit
whether there are tough manufacturing issues associated with implementing this process. If these new channels materials make an impact, it will open up a new era for the microelectronic industry, where new functions are integrated into chips. It may not be long, for example, until the time comes when multi-core CMOS chips could communicate between cores
with light via integrated III-V lasers, while making use of terahertz frequencies. So the promise of hybrid chips is awesome. However, as yet no one knows quite when – or exactly how – this is going to happen.
© 2014 Angel Business Communications. Permission required.
Further reading C. Marchiori et. al. J. Phys. D: Appl. Phys. 47 (2014) 055101 (2014) L. Czornomaz et.
al.IEDM Tech. Dig., 2.8, pp. 52-55 (2013) L. Czornomaz, et. al. 43rd IEEE ESSDERC Proceedings, pp. 143-146 (2013) N. Daix et. al. IEEE S3S Proceedings, in press (2013) L. Czornomaz et. al. IEDM Tech. Dig., 24.3, pp. 517-520 (2012) L. Czornomaz et. al. 70th IEEE DRC, 207-208 (2012) M. El. Kazzi et. al. Appl. Phys. Lett. 100 063505 (2012) L. Czornomaz et. al. Solid-State Electronics 74 71 (2012)
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