TECHNOLOGY LOGIC


substrate that uses a thin insulator to separate a 6 nm-thick InGaAs film from an 8 nm-thick SiGe layer on a silicon substrate (see Figure 2). This engineered platform has enabled both channel materials to be integrated on the same substrate for the first time, while matching the thickness requirements of the 14 nm technology node. This breakthrough should pave the way towards the production of dual-channel CMOS circuits, where n-type transistors could be built on InGaAs and p-type transistors on SiGe.


III-V challenges


As readers of this magazine all know, III-V materials have been used for many years for the manufacture of myriad RF/analog chips, LEDs, lasers, solar cells and high-power devices. However, although a lot of know-how has been developed and accumulated over several decades, none of these applications require the fitting of billions of devices onto an area the size of a fingernail – a requirement imposed by CMOS chips. This additional constraint forces engineers and scientists to revolutionize the way III-V devices


“


As readers of this magazine all know, III-V materials have been used for many years for the manufacture of myriad RF/analog chips,


LEDs, lasers, solar cells and high-power devices. However, although a lot of know-how has been developed and accumulated over


several decades, none of these applications require the fitting of billions of devices onto an area the size of a fingernail –


a requirement imposed by CMOS chips.


are fabricated, because gate lengths must be shorter than 20 nm, and, more importantly, contacts have to fit in less than 50 nm.


These pre-requisites cannot be met by turning to different lithography levels to define the different elements of the devices, because transistors are way too small. Instead, a so-called self- aligned process has to be developed that enables the construction of all the different building blocks of the device with a single lithography step: the gate definition. By taking this approach, device dimensions and device pitches can be aggressively scaled to meet the requirements of VLSI integration.


In 2012, the Zurich team showed that it is possible to fabricate self-aligned InGaAs transistors. These VLSI-compatible


Figure 3. (a) Cross-sectional TEM view of a “bulk” self-aligned InGaAs transistor on InP featuring high-k/metal-gate technology and raised source-drain. (b) Cross-sectional TEM view of an InGaAs transistor fabricated with the same process flow but transferred on a III-V- on-insulator on Si substrate. (c) Comparison of DIBL versus gate length for both types of transistors showing up to a factor of five reduction for devices on insulator


devices feature a gate-first high-κ/ metal-gate process with raised source- drain regions, which are just like those employed in industry for the manufacture of the most advanced silicon CMOS technology nodes.


The first ‘bulk’ transistors were fabricated on InP wafers (see Figure 3a), with successful operation down to gate lengths as small as 60 nm. The team then went one better, transferring the fabrication flow to III-V-on-insulator substrates on silicon, which had an InGaAs channel layer just 10 nm-thick


(see Figure 3b). ”


Within the SOI industry, it is well known that this class of engineered substrate offers a large performance boost, thanks to the confinement of the carriers in a very thin channel and better electrostatic integrity. Superior performance translates to a reduction in the drain-induced barrier lowering (DIBL) of the transistors by up to a factor of five (see Figure 3c). DIBL is a key figure-of-merit for the electrostatic performance.


Further accomplishments by IBM Zurich include the construction of InGaAs transistors with a 24 nm gate and a gate-to-gate spacing of just 300 nm (see Figure 4). To date, they represent the smallest, most compact VLSI-compatible InGaAs transistors reported on silicon.


Dual channel developments In addition to building standalone devices, the advanced dual-channel substrate technology can be used as a base for building small CMOS circuits. One of the benefits of this approach is that both channel materials are stacked on top of each other, so are present everywhere on the wafer. After defining some islands where transistors should be, the InGaAs channel can be removed to expose the SiGe channel where p-type devices are to be built (see Figure 5a). Although having both InGaAs and SiGe channels on the same wafer is an


January / February 2014 www.compoundsemiconductor.net 33


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