TECHNOLOGY LOGIC
the top of the trench. However, while this argument is applicable across the trench, where there is a high aspect ratio, it fails to hold true along the trench, where defects can propagate to the top channel material. This means that the channel material sitting on top of the trench is located on top of a defective semiconductor, which creates potential leakage paths from source to drain.
Figure 1. Comparison of the two main routes to integrate III-V on Si substrates: Aspect ratio trapping (on the left) and direct wafer bonding (on the right)
Efforts have now paid dividends: They have developed novel engineered substrates and process technologies for high-volume manufacturing in silicon foundries of VLSI circuits with compound semiconductor materials.
Silicon foundations
Although the microelectronic industry will have to undergo some big changes in the coming years, this will not include a change in substrate. So, to enable III-V and IV-IV compounds to be integrated in CMOS production, these materials will have to be introduced on a silicon substrate.
This is not easy, because integration of different, high-quality crystalline materials demands a matching of crystalline
arrangement and lattice constant. While InGaAs, germanium and silicon have a similar crystalline arrangement, their lattice constants are significantly different: Compared to silicon, the average atomic spacing is about 4 percent larger for germanium and 8 percent larger for InGaAs. It is possible to manage the lattice mismatch for SiGe and germanium with some engineering tricks, but this is not possible with InGaAs, because the mismatch between this alloy and silicon is far too high. If attempts are made to grow InGaAs directly on silicon, strain in the ternary is so high that this material relaxes by forming an excessively large number of crystalline defects, which would significantly degrade device performance.
Today, to overcome this defect-related weakness, industrial researchers are pursuing two approaches. One of the options is known as aspect ratio trapping, while the other – pioneered at IBM – is called direct wafer bonding (see Figure 1 for an overview).
Figure 2. Photograph and associated cross- sectional illustration of a high-mobility dual- channel substrate which comprises a 6 nm thick InGaAs layer on a 8 nm thick SiGe layer on a silicon handling substrate
Aspect ratio trapping exploits the defined angles of the crystalline defects. The starting point is to take a silicon substrate and etch out a narrow trench – that is, one with a high aspect ratio, or in other words a groove with a height that is several times greater than its width. When III-Vs are grown directly in this trench, defects form at the interface and propagate along defined angles, before terminating on the trench walls. Thanks to this defect-elimination process, a low defect InGaAs crystal is created at
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Aspect ratio trapping also restricts the availability of InGaAs. As this ternary is only present above the trenches, circuit designers are restricted in their positioning and sizing of the transistors. However, this issue disappears if the trenches can be tied together at a very small pitch, as required for the silicon fins of today.
Despite all these drawbacks associated with aspect ratio trapping, it still attracts a lot of attention, because it is directly compatible with silicon foundries that are now running 300 mm lines and could upgrade to 450 mm. However, foundries may find it much easier to pursue the technology that IBM is developing: direct wafer bonding.
With this approach, thin layers of III-Vs can be transferred onto silicon in the same manner already employed by industry to build silicon-on-insulator (SOI) substrates. Engineers simply grow the InGaAs layer on a donor substrate, before bonding it via an oxide to a target silicon substrate. The thin III-V layer is then released from the donor wafer to yield a III-V-on-insulator structure on silicon. This approach allows the donor wafer to be recycled, thereby maintaining the cost-efficiency of this process.
There are many attractive attributes associated with having a very thin III-V channel on an insulator. This combination is an ideal structure for maintaining good electrostatic control of the gate over the channel at short gate lengths, and it efficiently cuts leakage currents from source to drain. What’s more, this combination enables the use of the back-biasing technique, which permits dynamic adjustments of the transistor’s operation, so that it can be tuned to be faster or more power- efficient. All these merits reveal why III-V-on-insulator could be the preferred option for low power applications, such as mobile electronics.
The Zurich researchers have used wafer- bonding to create a hybrid, dual-channel
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