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March, 2014
Boundary Scan Integration on Flying Probe Testers
Continued from previous page
test had 331 nets and 335 components. The overall combined test time in this
Electronic & Engineering Materials
either decrease or increase. There are several factors that may influ- ence the overall test time, including
Ask about our IPC-CC-830 conformal coating designed for easy dip or spray application on printed circuit boards and surface mount devices.
Increase of coverage possible with flying probe and boundary-scan integration.
case increased by 16 percent. In the second case study, the
Learn more about our Conformal Coating Products
number of total nets on the board was 8915 and the total number of components was 5530. The overall combined test time in this case decreased by 37 percent. The flying probe and
314.621.5700
ww.elantas.com/pdg See at APEX, Booth 1025
boundary-scan test tech- niques have both been devel- oped to target the problem of net access in order to test cir- cuit boards. Comparison of the two techniques reveals weaknesses in both approach- es. Both techniques may run into net access issues. The speed of testing
with a flying probe tester is generally much slower than a boundary-scan tester when compared side by side for the same tests. Even though the ICs may be boundary scan compatible, a lack of DFT on the board may dramatical- ly decrease the net coverage when using a boundary-scan tester. Case studies reveal that combining the two techniques improves the overall test coverage on a circuit board. While the test coverage increas-
es when combining the two tech- niques, the overall test time may
Another view of integrating boundary-scan and flying probe testers.
decrease in test time. Instead, an analysis will have to be performed for each circuit board to fully assess the outcome. Contact: SPEA America, 2609
SSW Loop 323, Tyler, TX 75701 % 903-595-4433 fax: 903-595-5003 E-mail:
sales@speaamerica.com Web:
www.spea.com r
See at IPC/APEX Booth #701. For Electronic Assemblies,
Reliability Rules Continued from page 60
dards and replace them with lower, more conservative standards. The current IPC pass/fail stan-
dard for post-reflow cleanliness is 10 µg NaCl (eq)/in.2 (1.56 µg NaCl/cm2). A more realistic approach to cleanli- ness standards considers the compo- nent spacing on the assembly, the amount of electrical current, the cost of failure, and the climatic environ- ment (moisture) where the assembly will be functioning. By taking into consideration these four factors, one may determine the “safe” and tolera- ble amount of residues. For some assemblers, the cur-
rent IPC standard works well. These assemblies have measurable space between conductors, an adequate stand-off height less likely to trap residues, will be operating in a cli- mate-controlled/low humidity envi- ronment, and have a cost of failure that is not prohibitively high. For
other assemblers, fewer residues would be more prudent. Perhaps, in this context, the most practical defi- nition of the word “rule” is “a piece of advice about the best way to do something.” Contact: Aqueous Technologies
Corp., 9055 Rancho Park Ct., Rancho Cucamonga, CA 91730 % 909-944-7771 fax: 909-944-7775 Web:
www.aqueoustech.com r
See at IPC/APEX Booth #2063.
Michael Konrad (konrad@aque-
oustech.com) previously served on the U.S. Navy’s EMPF Manufacturers Committee in the late 1980s, and has published dozens of articles on clean- ing and cleanliness testing. He is a reg- ular speaker at industry conferences has taught cleaning and cleanliness testing workshops around the world.
the complexity of the circuit board, the design for testability, etc. There may not be an easy way
to tell ahead of time if combining the two test techniques will result in both an increase in coverage and a
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