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Boundary Scan Integration on Flying Probe Testers
By Zinnour Soultanov, SPEA America LLC, Tyler, TX
difficult access to test points. The increasingly small- er sizes of electronic devices drove the design of denser and more complex PCBs. The design con- straints in some cases, such as wireless-capable boards, dictated that minimal if any test pads would be placed on some circuit boards. Traditional in-cir- cuit-test (ICT) bed-of-nails testers could not provide adequate test coverage for these more complex cir- cuit boards mainly due to the loss of access to compo- nents and nets on the circuit boards. In response to these challenges of limited access for testing on PCBs, flying probe testers and boundary-scan testers were both introduced.
I
Flying Probe Technique Flying probe testers access PCB nodes
through multiple flying nails. Unlike bed of nails test systems, flying probe testers do not require test pads to make contact with nodes on a circuit
While a flying probe tester can
test the majority of the board using almost any contact point that is
not covered, boundary scan testing can provide levels of test impossible with probing alone.
board. In addition, a flying probe tester does not require a fixture, which results in a substantial cost savings advantage over bed-of-nails testers.
SPEA 4050 flying probe tester.
the testing. Since a flying probe tester relies on movement of the heads for positioning before mak- ing probe contact, the overall test time is slower compared to a traditional ICT bed of nails tester.
Boundary Scan Technique Boundary-scan testing became the IEEE
n the 1980s, the electronics test industry faced challenges related to more complex, densely pop- ulated printed-circuit boards (PCBs) and more
Since the fixture build was not required with flying probe programs, the time required for the test pro- gram to be ready for production also decreased dramatically. Typical tests performed on a flying probe sys-
tem include analog components tests, shorts test- ing, open pin testing, and optical measurements. Additional bias power may also be added as part of
1149.1 standard in 1990. The testing concept involves accessing the nodes of a circuit through boundary-scan cells that are built into the inte- grated circuits (ICs) on a PCB under test. To com- ply with the test standard, a device must include a four-wire (five-wire if optional reset signal is included) test access port (TAP), internal bound- ary-scan cells for each pin, associated internal boundary-scan registers, and additional multiplex- ing circuitry. In addition, the device vendor must provide Boundary Scan Description Language (BSDL) files that fully describe the boundary-scan implementation in the associated devices (JTAG Technologies B.V., 2008). Typical tests executed during a boundary-
scan test are interconnect test and infrastructure test. Cluster testing, memory testing, and flash programming are also available. The infrastruc- ture test is meant to find major connectivity prob- lems during a boundary-scan test. The intercon- nect test verifies the integrity of all boundary-scan testable nodes on the circuit board. A flying probe tester is capable of testing the
majority of the board using almost any contact point that is not covered. Examples of the points that a flying probe cannot access include back-to- back BGA pins, package on-package (PoP) pins, etc. On the other hand, a boundary-scan tester will be able to access some of the pins inaccessible to a flying probe tester, provided that there are bound- ary-scan cells available for those pins. A flying probe tester uses physical movement
of the probes to make contact with the circuit board. The physical movement of the probes dur- ing test contributes to the majority of test time. To
Continued on next page
March, 2014
See at APEX, Booth 2634
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