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February, 2020


What is JTAG and how can I make use of it?


JTAG is more than debugging and programming


You may be familiar with JTAG because you have used tools with a JTAG interface. Processors often use JTAG to provide access to their debug/emulation functions and all FPGAs and CPLDs use JTAG to provide


access to their programming functions.


JTAG is NOT JUST a technology for processor debug/emulation.


JTAG is NOT JUST a technology for programming FPGAs/CPLDs.


The debug and programming tools commonly associated with JTAG only make use of one aspect of the underlying technology – the four-wire JTAG communications protocol.


These four signals, collectively known as the Test Access Port or TAP, are part of IEEE Std. 1149.1. This standard was developed to provide a technology for testing Printed Circuit Board Assemblies (PCBAs) without needing the level of physical access required for bed-of-nails testing


Boundary Scan Register Boundary Scan Cells


Boundary Scan Test


Software Debug & Emulation


or the amount of custom development needed for


functional test. The TAP was designed to interact with new registers that were added to devices to implement this method of testing.


Very quickly however silicon manufacturers recognised the benefits of using the TAP to access registers offering other functionalities such as debug and programming.


In-System Programming


The main register added to a device specifically for JTAG testing is called the Boundary Scan Register (BSR). As its name suggests the individual bits, or cells, of this register are at the boundary of the device, between its functional core and the pins or balls by which it is connected to a board – very often JTAG testing is referred to as boundary scan.


How XJTAG uses JTAG / boundary scan to test a board


Boundary scan cells (see above) can operate in two modes. In their functional mode they have no effect on the operation of the device – this is the mode in which they operate when the board is running normally. In their test mode they disconnect the functional core of the device from the pins. By putting boundary scan cells into test mode they can be used to control the values being driven from an enabled device onto a net and also be used to monitor the value of that net.


Disconnecting the control of the pins from the Core Logic External Connections 1 Data In (TDI)


Programming Register Debug / Emulation Register


1


Control (TMS) Clock (TCK)


Instruction Register


Test Access Port (TAP) Controller


1 TRST* (optional) Data Out (TDO)


There are two main ways that this boundary scan capability can be used to test a board. The first way, connection testing (see next section) gives good test coverage, particularly for short circuit faults. It is based purely on the JTAG device capabilities, the connections and nets on the board and – in the case of XJTAG – the logic functionality on a board. The second way extends this coverage by using the JTAG enabled devices on a board to communicate with non-JTAG peripheral devices such as DDR RAM and flash.


functionality of the enabled device makes boundary scan test development significantly easier than traditional functional test as no device configuration or booting is required to use the pins. By providing a mechanism to control and monitor all the enabled signals on a device from a four-pin TAP, JTAG significantly reduces the physical access required to test a board.


enquiries@xjtag.com


Try XJTAG free today & get a free Test Setup with your trial See at IPC APEX, Booth 1423


www.xjtag.com/giveaway


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