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Engineered substrates  technology


Subsequent growth of GaN confirms this – the final centre-to-edge bow for this 200 mm diameter wafer was 54 µm concave (figure 8), a figure that satisfies silicon industry specifications for this size wafer. Complete strain management is possible, but this requires additional oxides.


Nonetheless, given that the silicon substrate was only 750 µm in thickness, this is a very encouraging result and confirms that REO templates offer a successful route to strain engineered GaN-on-silicon.


The deployment of multiple layers of oxides for strain management and improved device performance is not limited to LEDs; this form of architecture also promises to pay dividends in GaN-on-silicon power devices (see Figure 9 for an example of both structures). REOs combine a wide bandgap with a high value of permittivity – it is greater than 12 – and may allow an in-situ gate oxide to be deposited on top of a GaN FET stack witout breaking vacuum.


Capacitance-voltage measurements show minimal hysteresis, while breakdown testing reveals a consistent breakdown voltage of 4 MV/cm.


Figure 9. Oxide-based template engineering for strain, optical and electrical enhancement of silicon based III-N wafers.


It’s clear from these results with simplified LED and transistor structures that REOs offer great promise to improve device performance and trim manufacturing costs. The range of oxides is considerable. This means that there are many avenues – some still to be explored – for taking LEDs, transistors and solar cells to new levels of affordability and performance.


© 2012 Angel Business Communications. Permission required.


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