technology  Engineered substrates


substrate removal techniques, this process gets more complex and its cost becomes prohibitive as wafers scale to 200 mm and beyond. It seems that the concept of ‘chip and ship’ is rising in importance as the LED industry gains in maturity and volume through applications such as solid-state lighting. We have been able to construct high-quality, in situ embedded DBR mirrors on wafers with diameters of 50, 100, 150 and 200 mm. Alternating layers of epitaxially grown Gd2


O3 and silicon have combined


to form a DBR wafer with a peak reflectivity of 82 percent at 450 nm (see F. Erdem Arkun et al. Phys. Status Solidi C 9 814 (2012) for details of the growth of REO-based mirrors and their integration with GaN). Depending on design, stop bandwidths are typically in the range 60-80 nm and are highly suited to handling LEDs with light emission in the 440-470 nm range.


Scaling to large sizes


Figure 6. In-situ bow data from 300 nm REO thickness (top); and (b) in- situ bow data for 500 nm REO (bottom). Note that graphs are to scale


The promise of wafer processing at fully depreciated silicon fabs is a key value proposition for GaN-on- silicon technology. To spur this on, processes must be developed for manufacturing 200 mm flat wafers that can quickly win acceptance within the mature silicon industry.


What is meant by flat? Wafer bow must be below 100 µm over a 200 mm wafer. To meet this target, strain management must be accomplished as part of the epitaxy stack. This management must not be limited to single oxide layers, but must include more complex structures, such as DBR mirrors that include silicon layers.


Our efforts in this direction have included the growth of single layers of Gd2


O3


Figure 7. In-situ bow measurements of a three-pair REO- and silicon- based DBR mirror on a 200 mm silicon (111) wafer. Arrows indicate the compressive strain induced by each oxide layer as it is grown


with thicknesses of


0.1 µm-0.5 µm on 200 mm silicon (111) wafers. Measurements of bow were performed during the growth, before the wafers were taken out of the reactor and evaluated again.


Measurements on wafers with 300 nm and 500 nm oxides show that this layer induces convex bow (see Figure 6). This bow increases as more of the REO is deposited, revealing that it is possible to control the level of compressive strain in an oxide-based template by selecting the thickness of the oxide.


Figure 8. Ex-situ bow measurements of a three-pair DBR mirrors after growth of bulk GaN showing center to edge wafer bow of 54 µm


fabrication steps of removing silicon. The high reflectivity of the DBR prevents light emitted by the LED from being absorbed in the silicon substrate.


Although many manufacturers have demonstrated 40 www.compoundsemiconductor.net July 2012


Growth of oxide-based DBRs on 200 mm wafers produced similar results. During the deposition of alternating oxide and silicon layers with thicknesses of λ/4 and 3λ/4, the addition of every oxide layer imparts compressive strain to the multi-layer stack (see the arrows in figure 7). Note that this DBR is not fully optimized, due to a reduction in total oxide thickness. We have found that the silicon layers within the DBR result in some tensile strain, due to the different growth temperatures used in the multilayer structure. However, overall the direction is towards the desired compressive strain.


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