industry reliability
and then accelerate parts through their useful life span using environmental stressing techniques, introduced as aggressively as possible.
The primary goal was to induce all maverick fallout – without wearing-out the samples – and tally the risk at every stage in the OEM and consumer lifetimes of the devices. Since we had some experience with the failure mechanism, we were able to confidently select a group of reliability stresses with the best chance of inducing trauma that would simulate a customer’s lifetime of use (see table 1 for details).
We selected these stages based on the time frames that customers’ outline when describing their curiosity about reliability risks. Overarching these stages is a built-in expectation of defects for ‘normal’ (non-maverick) batches. The inherent expectation encompasses the relationships of quality assessments, made during manufacturing, and the reliability found in the consumer’s hands (see figure 1 for details). These expectations are built upon decades of experiences where quality is predictive of reliability. The normal situation is great, with reliability risk reducing at every stage in the life of an integrated circuit. What’s more, often the natural decreasing risk is even better than what we’ve portrayed here as ‘normal’, which is actually closer to defining the ‘boundary’ between acceptable and anomalous.
Scrutinizing lots With our plan, our expectation, and 30,000 samples in hand, we set out on a Friday morning to measure the risk of this special lot of material. By Monday, 150,000 measurements later, we had all the data we needed to precisely answer the tough question for this special lot. On top of that, we had identified a more general relationship, which would come to our aid when answering future questions about this type of scenario.
Even though we gathered most of the data in just one weekend, the results are compelling. That’s partly because we had such a massive sample to work with, and partly because our findings were matching the customer’s experience (so far) with their suspect population of devices. Armed with all this information, we could now provide a definitive answer to the specific question
Table 2.Risk assessment results
about risk. Our data enabled us to know what fallout to expect at each stage, plus the relative ratio of fallout to expect for this particular failure mechanism. The relative measure is highly valuable, because we can use the known ratio to make predictions, should other batches be found with different defect concentrations.
We found that it was very difficult to evoke the anomaly during manufacture with our normal suite of module tests. On the other hand, the OEM had the best detection, since their solder reflow process was 20 times better at exacerbating the fallout. The good news was that the fallout in the life stages following reflow was always lower than what the customer would see within their factory. So, in general terms, we could inform our customer that the worst fallout would occur in their factory, and the warranty risk to their customer was about half of the initial factory fallout and would be decreasing throughout the rest of the product’s life [1].
We continued to torture the samples with more aging and with multiple stress sequences to squeeze out every last drop of information. So within a few days of the initial weekend results, and after another 175,000 more measurements, the fallout eventually dropped to zero, giving us the final total of affected parts in our special lot… one half of one percent.
Wider implications To answer the broader questions customers can pose about detection and prevention of maverick lots, we must rewind the clock right back to 1998, when we first saw this mechanism returned from a customer [2]. At that time, we only had the customer’s returns to work with, so we studied the mechanism very hard. However, we could never re-create the root cause. What we did do was take preventive action, involving process improvements and design changes. In addition, we developed special test structures to detect the recurrence of this elusive defect. Twelve years on, the structures proved themselves worthy when we discovered a hike in the resistance on special monitors in several wafer lots – the old problem had come back!
Table
1.Plan for evaluating reliability of lifetime stages
In the initial re-discovery, we saw less than one-third of the wafers affected from three lots. The data indicated that the defect-
January / February 2013
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