conference report IEDM
Figure
5.Cross- sectional TEM image of a GeSn MOSFET produced by a collaboration led by researchers at Stanford University
image reveals that the GeSnOx
layer
formed by the oxidation process is just 2.6 nm thick
Taking these devices and producing them in foundries will be challenging. “The more complicated the structure of the device, the greater the problems of reliability and manufacturability,” admits Ye, who would be delighted to team up with an industrial partner to tackle these issues.
.This Options for the p-FET
They have now addressed these weaknesses by halving the thickness of the Al2
O3 gate dielectric
from 10 nm to 5 nm, which has improved electrostatic control. In addition, they have boosted the mobility in the channel by switching the composition from In0.53
Ga0.47 As to In0.65 Ga0.35 As.
Thanks to these changes, typical values for sub- threshold swing in devices with a 50 nm long channel have fallen from 150 mV/decade to just under 100 mV/decade, while DIBL has plummeted from 210 mV/V to just 50 mV/V. Transconductance has also risen, hitting 1.1 mS/µm at a drain-source voltage of 0.5 V.
Results for the four-dimensional transistors, which sport an In0.53 Al2
Ga0.47 O3 As channel and a 10 nm-thick
gate dielectric, are also encouraging. Measurements on a transistor with a 4 by 3 nanowire array with 200 nm long channels produce a transconductance of 0.6 mS/µm at a drain-source voltage of 0.5 V. This value, plus that for the perimeter-normalized drive current, are similar to those produced by the three-dimensional transistors described at IEDM 2011.
More recently, these engineers from Stanford have developed a complimentary electron channel in collaboration with researchers at imec, KULeuven and GlobalFoundries. According to corresponding author of the paper detailing this work, Suyog Gupta, the attraction of using GeSn for the n-channel – rather than the likes of InGaAs – is that it enables a ubiquitous platform for seemless integration of CMOS logic and silicon-compatible photonics (see Figure 4). “We intend to use germanium tin as a single material platform of high- performance logic and optoelectronics,” explains Gupta, who points out that this alloy is the only group IV material with a direct bandgap, which makes it a very attractive candidate for providing light emission.
One of the biggest challenges facing the pioneers of germanium and GeSn nMOSFETs is to develop a process that yields high-quality surface passivation. “We have solved this issue for both germanium and germanium tin and achieved a very low high- K/semiconductor interface trap density,” explains Gupta. Fabricating high-quality gates begins with ALD of a 1 nm-thick layer of Al2
O3 or GeOx . Oxidation at
400 °C in ozone then creates an interfacial layer of GeSnOx
according to cross-sectional transmission electron microscopy images (see Figure 5). These gate stacks have a high-quality interface, according to plots of capacitance as a function of voltage that show negligible frequency dispersion in depletion and accumulation.
Figure
6.Germanium pMOSFTS and InGaAs- on-insulator nMOSFETs have been built side- by-side on germanium substrates by engineers at the University of Tokyo
38
www.compoundsemiconductor.net January / February 2013
Gupta explains that one of the benefits of the improved passivation process is enhanced electron mobilities in the nMOSFETs. The room-temperature mobilities in the team’s transistors, which contain between 6 percent and 8.5 percent tin, can get close to 400 cm2
V-1 s-1 . However, electron mobility in these devices is still inferior to those with , which has a thickness of 2.6 nm,
Although germanium is the leading candidate for the hole channel, SiGe and GeSn could yield better results. The latter enables an increase in hole mobility: According to a IEDM 2011 paper presented by a team headed by researchers at Stanford University, switching from a germanium channel to a GeSn alloy with just 3 percent tin boosts hole mobility by 20 percent.
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