conference report IEDM
Into the fourth dimension
The four-dimensional transistors that are being pioneered by Peide Ye’s team at Purdue University feature a two-dimensional array of InGaAs nanowires. Fabrication begins with the growth of epiwafers on InP substrates. This involves deposition of a 10 nm-thick undoped InAlAs etch stop layer, followed by an undoped 80 nm InP sacrificial layer and a stack of pairs of InP and InGaAs layers: three In0.53
As channel layers that are 30 nm thick, sandwiched between 40 nm InP layers. Uniform doping of the source and drain contacts is realized by a two-step silicon implantation process, using energies of 20 keV and 60 keV and a dose of 1 x 1014
Ga0.47 cm-2 .
Dopant activation resulted from rapid thermal annealing in nitrogen gas for 15 s at 600 °C.
A 10 nm-thick Al2 O3 hard mask, deposited by atomic layer
deposition (ALD), paved the way to the formation of fins with a height of 200 nm. These were defined through etching in a mixture of chlorine gas and oxygen, a pairing that is superior to BCl3
for
yielding high quality sidewalls. Subsequent etching in a solution based on hydrogen chloride released the nanowire arrays, before the structure was passivated in 10 percent (NH4
)S2 O3 . After this step,
at 300 °C, followed by the growth of WN at 385 °C. The last steps of the fabrication process involved etching to form the base in a mixture of methane and oxygen, and electron beam evaporation of Au/Ge/Ni, followed by lift-off to define source and drain contacts. After forming the source/drain alloy at 350 °C, Cr/Au test pads were defined.
germanium channels. That’s because the mobility is held back by growth on relaxed germanium buffers, which cause the GeSn to be under biaxial compression, due to its larger lattice constant than germanium. “The compression is one of the reasons why we see an improvement in hole mobility [when switching from germanium to germanium tin],” explains Gupta, who reveals that this strain also reduces the speed that electrons zip through the material. The next step for the team is to form relaxed GeSn. “We believe that this is important, since we expect relaxed germanium tin to show performance enhancements over germanium.”
Improving gate stacks Very little work has been carried out so far on the unification of post-silicon nFETs and pFETs. This has been accomplished on a germanium platform by a team from the University of Tokyo headed by Shinichi Takagi and Mitsuru Takenaka (see Figure 6), and at the most recent IEDM they reported electron and hole mobilities of 1800 cm2 and 260 cm2
V-1 V-1 s-1 s-1 , respectively. This represents
electron and hole mobility enhancements of 250 percent and 130 percent, respectively, compared with silicon.
the wafers were immediately loaded into the ALD tool for deposition of Al2
Takagi explains that this work is in its infancy: “In this feasibility study the channel length is pretty long. It is 50 or 20 micrometres, though shorter channel devices are also operating.” The operating voltage for these devices is about 2 V.
The paper that they presented at IEDM details a number of recent breakthroughs, including the development of germanium nMOSFETs and pMOSFETs. Built on native substrates, this pair of transistors combined very high mobilities for this material system with very few interface traps and a low EOT. For example, transistors with an EOT of just 0.82 nm and 0.76 nm have produced electron mobilities of 754 cm2 690 cm2
V-1 V-1 s-1 .
They key to all this success is the novel process for producing the gate, which is a stack of HfO2 GeOx
, Al2 film of Al2 , before oxygen plasma treatment
creates a GeOx GeOx
O3 ,
and germanium. ALD is used to deposit a thin O3
does not get too thick, because the Al2
film under this layer (see Figure 7). O3
as an oxygen barrier, and experiments by the team have shown that just 0.5 nm of GeOx
can reduce
the density of interface traps. The addition of HfO2 needed, because Al2
O3 has a relatively low January / February 2013
www.compoundsemiconductor.net 39 is acts s-1 and
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