Sheraton Frankfurt Airport Hotel 04 March
without compromising the performance or yield currently obtained on sapphire or smaller size silicon substrates. The technology must provide high-yield growth of GaN devices on large area substrates meeting the fundamental physical challenges of a strong wafer bow and crack formation as well as the reactivity of Ga with Si.
How does it solve the problem? Based on extensive numerical simulation, new hardware components and processes were developed. A novel gas inlet was designed that provides unmatched gas phase stability and controllability. The setup delivers excellent process reproducibility uniformity and yield on the full area of all 200 mm wafers. Furthermore temperature management was adapted to the requirements of the large area GaN-on-Si process.
Special focus was put on the bow management. The reactor minimises the vertical heat flux through the wafer which results in the lowest wafer bow. The specific geometry of the reactor provides rotational symmetry of the GaN films. Additionally, a reliable method to reset all chamber conditions was developed meeting the challenges of the Ga-Si chemistry.
ARC Energy CHES furnace for sapphire crystal growth
CHES furnaces for sapphire crystal growth use a new technology called Controlled Heat Extraction System. CHES technology furnaces convert more than 75% of the sapphire grown into product which is c-axis sapphire for light emitting diodes (LED) applications. This is compared to 10-35% for conventional technologies. This means CHES furnaces are able to supply High Brightness LED manufacturers with much more efficient sapphire substrates at reduced costs.
This material utilisation improvement was needed as the industry proceeds towards larger diameter substrates. CHES furnaces achieve this efficiency with three features.
Firstly, sapphire is grown on the c-axis of the crystal which matches the orientation required for HB-LED manufacturing. This saves the wasteful method of coring from the side of the boule which results from a-axis growth (process utilised by conventional technologies).
Secondly, CHES furnaces create sapphire boules that are near net shape. This allows further savings and can allow for eliminating the coring step as the outer diameter can be simply ground to shape.
The third feature is very low defect levels. The presence of defects is a major challenge for conventional sapphire growth technologies and greatly reduces yield when growing for large diameter applications. Another benefit to CHES is less bow and
warp during epitaxy. In the MOCVD reactor excess bow and the presence of warp can dramatically reduce LED chip yield. CHES achieves low warp due to the wafers being sliced from a layer of the boule that was grown in a short time creating a single heat time signature. In addition to the growth advantages, CHES furnaces use a high level of automation for crystal growth.
This has dual advantages: less operator training costs and higher consistency in the growth process. These features make CHES furnaces a key technology in reducing HB-LED costs.
What industry challenge does this address? Sapphire crystal growth has been on-going for about 100 years and it was used as a specialty product because it was expensive. The industry had problems in growing c-axis sapphire hence a-axis was commonly grown. Product requirements of c-axis were cored perpendicular to the growth axis of a-axis crystals.
LED application requires c-axis sapphire substrates in very large quantities. ARC Energy made a paradigm shift by focusing on c- axis sapphire growth and the result is CHES furnaces for sapphire crystal growth. All the above advantages followed.
How does this solve the problem?
CHES furnaces make sapphire substrates affordable and these economies increase with larger diameter sapphire. CHES furnaces operate with more than 75% material utilisation for large diameter. Competing technologies can only reach 10-35% and this yield decreases with larger diameter sapphire. CHES furnaces can today supply the HB-LED industry with the large diameter substrates required to reduce solid state lighting (SSL) costs.
Using 2-inch diameter substrates as baseline for a single MOCVD run 6-inch sapphire provides 55% more LED chips and for 8-inch the advantage is 77%. This represents a dramatic improvement in cost savings for LED chip manufacturing.
January / February 2013
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