Compound Semiconductor January/February 2013

conference report  IEDM

variants: “An important concern for the III-V FinFET is dry-etching damage, which is difficult to anneal in compound semiconductors. Nevertheless, at the 10 nm gate length regime, the FinFET geometry might be the only one that can deliver the required combination of performance and short-channel effects.”

From 3D to 4D

Figure 3.Peide Ye’s team at Purdue University have refined the architecture of their three- dimensional III-V transistors by introducing a two- dimensional array of channels.A top-view of these devices,known as 4D transistors,is provided in the top left image.The top right image shows a cross-sectional SEM image of an InGaAs/InP fin structure fabricated by dry etching,using a hard mask made from Al2

O3

and grown by atomic layer deposition.Bottom left: Cross-sectional image shows a 3 by 1 InGaAs nanowire stack.Bottom right: A 3 by 4 nanowire array

turn off sharply. Further improvements could be possible, because a similar device with a 300 µm gate produces a sub-threshold swing of just 69 mV/decade.

The team have compared the performance of their gate structure with an Al2

O3 O3 gate dielectric. Plotting

capacitance as a function of voltage reveals features that are indicative of slow traps close to the mid-gap in the Al2

the structure containing HfO2

-based device – these are not present in . This is encouraging,

but Lin insists that there is still more work to do: “We need to reduce trap levels to where not only the best performance, but also the best reliability, can be obtained.”

Intel’s launch of three-dimensional transistors could signal a departure away from the use of the traditional, planar MOSFET architecture to build microprocessor chips. However, Lin argues that the phasing out of planar devices is not a foregone conclusion: “Many papers from industry at the latest IEDM have reported competitive results on planar, ultra-thin-channel silicon-on-insulator FETs. It remains a question which one, or both, will prevail.”

Lin claims that the recent work at MIT demonstrates that planar III-V MOSFETs with a thin channel can offer strong competition to three-dimensional

Figure 4.A research team led by engineers at the University of Stanford is developing GeSn MOSFETs.Compressive strain can boost the mobility of holes in the p-channel,while tensile strain is needed to enhance electron mobility in the nFETs

January / February 2013 www.compoundsemiconductor.net 37

One of the pioneers of three-dimensional III-V MOSFET is Peide Ye from Purdue University. His group, working in collaboration with researchers at Harvard University, have recently improved the performance of their gate-all-around nanowire MOSFETs, and also taken them in a new direction that they refer to as the fourth dimension – this involves stacking the nanowires horizontally and vertically (see box “Into the fourth dimension” for details of the architecture of the device and how it is made, and Figure 3 for images of this structure.)

“The 4D transistor, in principle, can boost drive current and keep the best electrostatic control by the gate-all-around design,” says Ye. He believes that this device delivers the drive current required for the 11 nm node, but its off-state performance needs to be improved.

Advances in the performance of three-dimensional transistors and the introduction of four-dimensional variants build on the work presented by Ye’s team at IEDM 2011. At that meeting in Washington DC they unveiled the first III-V gate-all-around nanowire MOSFETs, which had a relatively high EOT that limited the device’s transconductance, sub- threshold swing and drain-induced barrier lowering (DIBL). The DIBL is an important figure of merit, because it provides an insight into the electrostatic integrity of the device, and how its performance will be impacted by shrinking device dimensions.

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