conference report IEDM
Figure
7.Researchers at the University of Tokyo create GeOx below Al2
films O3 layers via
oxidation with an ECR oxygen plasma
standby power applications,” explains Takagi. “So, although 0.76 nanometres might not really be enough for high-performance applications, it is pretty close.”
Takagi and his co-workers have also developed a process for forming germanium-rich MOSFETs on silicon substrates (see box “Building on silicon” for details of this process). This creates a highly strained channel, helping to enhance hole mobility to a value eight times higher than that found in silicon MOSFETs.
permittivity, and limits the EOT to 1 nm. Just using HfO2
on top of GeOx is not an option, as these
layers intermix, creating an interface with many traps.
Creating a HfO2 /Al2 O3 /GeOx /germanium stack leads
to an EOT of just 0.76 nm. “According to the ITRS 2011 [roadmap], EOT at the 11 nm node is 0.76- 0.61 nanometres for high-performance applications, 0.86-0.75 nanometres for low operating power applications and 1.1-0.9 nanometres for low
Building on silicon
Researchers at the University of Tokyo have recently developed a process to form germanium-based pMOSFETs on strained silicon-on-insulator (SOI) substrates. Fabrication of devices begins by taking a SOI substrate, depositing a thin film of silicon on this, and adding a layer of SiGe on top of that (left). This wafer is then oxidized at high temperature, and during this process silicon atoms are preferentially oxidized to form a SiO2
film, while germanium atoms are rejected and transferred to the SiGe film (middle).
When InGaAs, rather than germanium, is used for the electron channel, the indium content is often used to adjust the strain and ultimately the mobility. Takagi and co-workers, however, have been able to decouple the influence of strain from the impact of adjustments in InGaAs composition. “We have changed the strain under a given indium content by using relaxed InGaAs buffers with different indium contents, allowing us to extract the effect of strain on mobility.”
The team from Tokyo have formed these transistors on silicon. One way to do this is to etch narrow trenches in silicon wafers, and deposit material into these groves to form the channel of the device. Takagi says that in terms of productivity, this approach is the most attractive option, because the only additions to the CMOS process are selective growth processes. “The difficulty [with this approach] is the channel material quality – the lattice mismatch between silicon and both III-Vs and germanium is so large, and so many defects can be introduced into the channels. Aspect ratio trapping can mitigate the density of dislocations, but the material quality has not been proven yet.”
Direct wafer bonding Takagi and his co-workers have taken a different approach to forming III-V transistors on silicon – direct wafer bonding. This “guarantees” material quality, says Takagi, but he adds that it impairs productivity and probably leads to higher production costs. Another downside of this approach is that it is challenging to realize selective formation of III-Vs and germanium on silicon, and this could constrain chip design.
The buried oxide (BOX) layer prevents germanium atoms from diffusing into the silicon substrate, leading to a steady increase in the germanium content in this layer. Meanwhile, silicon atoms in the SiGe layer diffuse to the interface with SiO2
a pure film of germanium can be formed (right). 40
www.compoundsemiconductor.net January / February 2013 . Once all the atoms of silicon above the BOX are oxidized,
Lukas Czornomaz from IBM Zurich Laboratory agrees with Takagi that direct wafer-bonding delivers very high material quality, and claims that it is the most mature technology for wafer scale formation of III-V and germanium transistors on silicon. “Direct wafer bonding will be the first to allow a proper technology evaluation at dimensions and densities which are relevant for the semiconductor industry.”
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