conference report  IEDM


Figure 1.Researchers at MIT have fabricated InAs quantum well transistors with a gate length of just 22 nm (left).A high-resolution transmission electron microscopy image reveals the high material quality of this stricture (right)


However, before these materials can make an impact at the 11 nm node, which will be introduced in foundries in 2018, several questions must be answered: Can III-V and germanium transistors work well at this length scale? What stack of materials should be used to insulate the gate from the channel? What transistor architecture should be adopted? And how should these transistors be formed on 300 mm silicon, which is the only substrate that can be considered, because billions of dollars of foundry equipment has been built around it.


At the International Electron Devices Meeting (IEDM) in San Francisco that was held from 10-12 December 2012 engineers from a variety of backgrounds offered answers to all these questions. Contributions from delegates included: Promising device results on InGaAs MOSFETs with a gate length of just 22 nm; new architectures for boosting drive current; improved gate dielectrics for electron- and hole-conducting channels; and wafer-bonding technologies for forming III-V transistors on a silicon substrate.


Shrinking the gate


The team that has pioneered the fabrication of III-V MOSFETs with incredibly short gate lengths is Jesús del Alamo’s group at MIT (see Figure 1). These engineers have built planar InAs quantum well MOSFETs with a HfO2


gate dielectric that


produce encouraging performance at an operating voltage of just 0.5 V.


Corresponding author of the IEDM paper detailing this effort, Jerome Lin, believes that there are four important aspects to the team’s work. “First of all, it’s scalability,” argues Lin. “For the lateral scaling, we have demonstrated III-V MOSFETs with the smallest gate lengths so far. They deliver fast electron transport and electrostatic integrity down to a 30 nm gate length.” In addition, he says that these devices have shown that vertical scaling is possible. “In order to have the required electrostatic integrity to meet the short-channel-effects goal, we have developed an advanced gate stack.” This has an equivalent oxide thickness (EOT) of less than 1 nm.


The second important aspect to MIT’s work is the self-aligned contact metal process. Lin claims that although this is essential for making a CMOS device, it rarely features in the fabrication of III-V MOSFETs.


According to Lin, the two other breakthroughs described in his paper are the promising performance of the gate barrier and a fabrication route using a “MOS-like” process. “In the front-end, the process is lift-off free and gold-free.”


The team produced its planar devices on MBE- grown, InP-based epiwafers from Intelliepi. These structures feature a complex, 10 nm-thick channel with a 2 nm InAs core, clad by 3 nm and 5 nm layers of In0.7


Ga0.3 As. Processing began with the


sputtering of molybdenum onto these epiwafers, followed by CVD deposition of SiO2


, mesa isolation,


and the formation of the gate pattern via electron- beam lithography. Reactive ion etching (RIE) patterns the molybdenum and SiO2


layers, before


annealing in nitrogen gas removes RIE damage. A variety of etching techniques then removes some of the epilayers, including a technique that involves plasma oxidation and dilute sulphuric acid. This removes about 0.9 nm of InAlAs or InP per cycle.


With this approach, the team can leave just 1 nm of InP above the channel. Onto this they add 2 nm of the dielectric HfO2


Evaporation of molybeum creates the gate contact, which is patterned by RIE and has a gate length defined by the recess opening in SiO2


by atomic layer deposition (ALD). . A pad formation


process, which finishes device fabrication, is the only lift-off step. It occurs at the backend of the process.


Figure 2.The


sub-threshold swing of MIT’s planar InAs quantum well transistors is comparable to Intel’s Tri-Gate devices


36 www.compoundsemiconductor.net January / February 2013


Transistors operating at 0.5 V and featuring a 30 nm gate length produce a transconductance of 1420 µS/µm. Electron channel mobility is 4650 cm2


V-1 s-1 in long channel transistors. Sub-


threshold swing in these planar devices is just 114 mV/decade, which matches the best finFET III-V devices and is superior to any other planar MOSFET (see Figure 2). Having a low sub-threshold swing is highly desirable, because it enables the device to


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