This page contains a Flash digital edition of a book.
July, 2017


www.us-tech.com Copper Pillar Bumped Flip Chips: Part 2 Continued from previous page


than the sample with the positive mean stress. There are several anecdotal


observations of this tensile effect in electronic packaging. The most well- known is the failure of Nvidia GPU devices. With guidance from several publications on the effect of tensile stresses, researchers have showed the effect of repeated excursions through the Tg.


Intermetallic Growth Another area needing study and


experimental validation is the growth of significant volumes of intermetallic in the solder portions of the copper pil- lar joint. Investigations have shown elevated volumes of Cu3Sn and Cu6Sn5 intermetallic within the sol- der portion of the joint, especially after exposure to high temperature storage (HTS) or thermal cycle conditions. The presence of intermetallic


particles can improve creep resistance, and therefore thermal fatigue perform- ance. This is why SAC405 performs better than SAC305 and SAC205. At the same time, high volumes of brittle intermetallics in the joint could make it brittle, possibly degrading its resist- ance to shock and vibration. The thermal fatigue lifetimes for


copper pillar joints need more study, particularly experimentally. Details of the interconnect design and process will likely lead to a wide variety of per- formance over the broad range of cop- per pillar packages. Further, consis- tency of the solder between the copper pillar and bond pad becomes critical. For example, wetting along the sides of the copper pillar can result in a very thin bondline, likely jeopardizing per- formance. Insufficient coplanarity of the


copper pillars also can result in joints of non-optimal geometry; the copper plat- ing process can result in pillar heights that vary by as much as 25 percent, or 40 to 50 µm. Finally, in some cases, use of copper pillar could even shift the fail- ure location under thermal cycling, which might not be detected in a sin- gle-environment experiment.


Dielectric Cracking Cracking of the silicon dielectric


layer is of increasing concern as the electrical requirements drive chip designers to extra low-k (ELK) and ultra low-k layers. In fact, ELK layer cracking is often viewed as the biggest risk in the transition to cop- per pillar. The primary concern is during the flip chip bonding process, with some observations of cracking during underfill cure. The challenge is to identify mitigation techniques through materials, interconnect design and assembly processing. Such techniques may require com- promises relative to other potential failure modes, such as thermal fatigue of the solder. Tall copper pillars help to decou-


ple the interaction between the pillar and the dielectric layer, but is a tradeoff since taller pillars require more plating time, decreasing throughput, and may increase stress in the joint. Copper pillar first-level inter-


connect technology is increasing in popularity as a means to address decreasing feature sizes on the sili- con, form factors for mobile devices and other technical challenges in modern flip chip devices. Copper pil-


smt.hanwhatechwin.com LED Big Board Solution


An increase in accumulated viscoplastic strain energy density per thermal cycle of copper pillar joints vs. conventional interconnects.


lar technology can overcome the inherent size limitations of solder bumps (limited to about 150 µm pitch or larger). The efficacy of copper pil- lar has already been demonstrated down to sizes of 80 µm and appears to be a promising approach down to pitches of 40 µm. While copper pillar interconnect


technology is certainly here to stay, much more study is needed regarding the reliability of the different types of package and pillar technologies. Contact: DfR Solutions, 9000


Virginia Manor Road, Suite 290, Beltsville, MD 20705 % 301-474-0607 E-mail: sales@dfrsolutions.com Web: www.dfrsolutions.com r


Page 63


Production class assembly equipment for 24”, 28”, 48”, 59” PCB form factors includes high performance printing, precision component mounting, repeatable reflow, and reliable board handling with expert training, service and support.


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56  |  Page 57  |  Page 58  |  Page 59  |  Page 60  |  Page 61  |  Page 62  |  Page 63  |  Page 64  |  Page 65  |  Page 66  |  Page 67  |  Page 68  |  Page 69  |  Page 70  |  Page 71  |  Page 72  |  Page 73  |  Page 74  |  Page 75  |  Page 76  |  Page 77  |  Page 78  |  Page 79  |  Page 80  |  Page 81  |  Page 82  |  Page 83  |  Page 84  |  Page 85  |  Page 86  |  Page 87  |  Page 88  |  Page 89  |  Page 90  |  Page 91  |  Page 92