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Page 54 Machine Learning: A Logistical Advantage Continued from page 52

joints, but can also infer much more. With access to information, including BSDL files for the JTAG- enabled devices on the PCB, as well as (but not necessarily) the board’s netlist and BOM, the soft- ware can determine the presence and correct ori- entation of components. The ability to access the chip registers of a device through JTAG- controlled components can allow confirmation that the right component has been fitted and that it is functioning. It should be apparent that, even for a sim-

ple board, creating a test pattern to exercise accessible nets, interrogate devices on the board, and interpret the results is complex. Of course, understanding how the nets on a board are interconnected and optimizing the test pat- tern in response to that can significantly reduce the number of tests executed and there- fore accelerate the overall test process. This should be considered when evaluating

gramming (ISP). This uses the access provided by the JTAG interface to not only test, but also pro- gram devices on the board, often in a single process. ISP is also a feature supported by most FPGA vendors using their own software and hard- ware. However, commercial JTAG vendors are

Assistance can now be provided with both of these aspects. PCB designers using Altium Designer, Mentor Graphics PADS or Cadence’s OrCAD Capture can now verify the scan chain from within the CAD tool. Plug-ins provided by JTAG vendors, such as XJTAG and JTAG Technologies, automate the process of verifying the scan chain. This involves checking that the TAP

signals are routed to the correct pins on all JTAG-enabled devices. The plug-ins can also display the level of test access that can be achieved using the respective vendors’ tools. Designers can then take steps to ensure the TAP is routed and terminated correctly and that test access is maximized, during the schematic capture stage. This can greatly reduce the need for PCB re-spins. In terms of maintaining signal integri-

the technology available from commercial ven- dors. While maximum theoretical test coverage is based on the board design and therefore beyond the control of JTAG test equipment vendors, the actual coverage attained and the ease with which tests can be created and executed is entirely under their con- trol.

and software equipment on a trial basis in order to allow engineers to assess it using their own boards, and draw their own conclusions. The best will even offer to do the board set up free of charge.

Functional Test and ISP It is also well within the scope of commercial

JTAG test software to develop functional tests for the active devices on a PCB, as well as use the func- tionality of non-JTAG devices to extend test cover- age. This is normally achieved by writing tests which use the functionality of a device. These tests are often created by the JTAG equipment vendor and supplied in test libraries, although most tools also provide a way for creating custom tests. Another major use of JTAG is in-system pro-

Diagram of good practice in JTAG chain implementation.

able to support ISP of almost any non-volatile device, as long as it is accessible from a JTAG- enabled device. An example is XJFlash from XJTAG. It

Most JTAG providers will loan their hardware

enables flash-based memories connected to FPGAs to be programmed in-system at much higher rates than with a conventional JTAG approach. It has also been extended recently to support the ISP of FPGAs with dual-ARM processor architectures, now available from multiple FPGA vendors.

Making JTAG Work A JTAG interface comprises five signals, four

of which are mandatory, collectively known as a test access point, or TAP. As the bus is daisy- chained between devices, the data out signal of one device becomes data in for the next in the chain. The TAP needs only one point of access to a board, typically through a small connector or header. There are two critical aspects to getting suc-

cessful implementation of the JTAG scan chain on a PCB: routing the TAP between devices, and main- taining the signal integrity of the TAP signals.

ty, XJTAG’s plug-in can also verify that suit- able pull and termination resistors have been added to the TAP signal nets. The plug- in also verifies that other pins which are

needed to put JTAG devices into their test mode are not hardwired to the wrong values. JTAG has been present in ICs for nearly

three decades and shows no sign of being supersed- ed by any other technology. In fact, it is evolving to ensure it will continue to meet the needs of design- ers and OEMs. Currently, it can be used to check test access

at the schematic stage, help debug prototypes, locate manufacturing defects, program non- volatile devices and even functionally test PCBs; in the future it will be used to embed virtual test equipment and improve support for testing differ- ential signals. It goes far beyond simply being a debug inter-

face, and the work taking place within the IEEE ensures it will remain an active and progressive technology for years to come. Contact: XJTAG, St. John’s Innovation

Centre, Cowley Road, Cambridge CB4 0DS, UK % +44-0-1223-223007 fax: +44-0-1223-223009 E-mail: Web: r

July, 2017

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