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Page 52

July, 2017

Beyond Debug: XJTAG for Flash Programming and Board Test

By Philip Ling T

he JTAG standard, first established by the IEEE 27 years ago, defines an electrical and physical method for connecting JTAG-enabled

devices on a PCB, or across multiple PCBs. However, JTAG is not a general-purpose bus. The technology behind the interface differs significantly from a standard communications interface. The JTAG subsystem inside a JTAG-enabled

device is empowered to take control of the pins of that device. In this mode the device’s primary func- tions are suspended, enabling the JTAG subsystem to assert or read each pin’s logic level, in response to messages sent over the JTAG scan chain. It effectively turns every pin on the device

into a virtual test point, accessed electronically, which is extremely useful for debugging a proto- type board. These virtual test points, accessible without a dedicated test fixture, mean that even first prototypes can be tested using JTAG, on a bench or even by the manufacturer. Each device in the scan chain is characterized

by a description file written in boundary scan descriptive language (BSDL). Silicon vendors pro- vide a free BSDL file for each type of JTAG- enabled chip. This file describes the JTAG capabil- ities of the device. Test data sent to the JTAG scan chain is seri- ally clocked in and out of each device, typically at

JTAG effectively turns every pin on the device into a virtual test point, accessed electronically.

several MHz. The speed at which boundary scan tests can operate often comes down to how well the scan chain has been implemented on the PCB in terms of signal integrity, as well as the capability

JTAG goes beyond being simply a

debug interface, and can perform flash programming as well as a range of tests.

JTAG for Test Automated test equipment (ATE), such as in-

circuit test or flying probe machines, relies predomi- nantly on having physical test access points. Many ATE machines now claim JTAG support, but some only use it to verify the existence of components that offer little or no access for conventional test probes. Some vendors, however, are serious about interoperating with each other to produce an opti-

and efficiency of the test equipment used. This is how JTAG tool providers are able to differentiate themselves, in how well their technology can gen- erate test patterns, apply those tests, interpret the results and reformulate new test patterns to iden- tify and isolate fault conditions quickly.

mized set of tests that maximizes coverage while minimizing test time and fixture costs. This presents an opportunity for specialists in

this field, to offer technology that produces high- speed, optimized tests, and some of the leading ATE and JTAG vendors can perform such opti- mizations.

Test Coverage The purpose of any automated test or inspec-

tion equipment is to locate and, if possible, identi- fy manufacturing defects. Some defects could be design-related (e.g. the PCB may have been assem- bled correctly but the circuit’s function is inherent- ly wrong) but the EDA tools now available help ensure that a design can at least be tested as soon as the first prototype is manufactured. Performing suitable design-time checks also

saves engineers vast amounts of time writing cus- tom functional tests at the board bring-up stage because full JTAG testing is available to diagnose issues much more quickly. The extent to which a PCB can be tested for

such defects, and therefore the effectiveness of any test equipment in finding those faults, can be measured. For any given PCB that figure will depend on the number of devices, the number of pins and the level of test access. For ATE that relies on physical test access,

the lack of test access points will lower that figure. JTAG can be and is used to significantly increase test coverage achieved by ATE, but it can also be used as a standalone alternative, addressing all of the recognized parameters for measuring and pro- viding test coverage. At the most basic level, JTAG testing can identify defects, such as open or short circuits on Continued on page 54

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