TECHNOLOGY VLSI SYMPOSIUM
remainder of the 12 nm-thick spacer and heavily doped In0.53
Ga0.47 the source and drain.
Using MBE processes for the creation of epiwafers for VLSI is not ideal, due to high costs and the challengers of growing uniform films over large wafers. “The reason why we are using MBE is that our MOCVD system has no aluminium source, so we cannot grow the indium aluminium arsenide barrier using MOCVD,” explains Lee. “To my best knowledge, InP-related material can be grown using MOCVD that is as good as MBE, in terms of epi-quality.”
To process the epiwafers into MOSFETs, device mesas were defined with a wet etch, before dummy gates were stripped in buffered hydrofluoric acid. A two-cycle isotopic digital etch then removed about 2 nm of the In0.53
Ga0.47 As cap and about
1 nm of the InAs to leave a 2.5 nm-thick channel. These wafers were immediately loaded into an ALD tool.
After in-situ nitrogen plasma/tri-methyl- aluminium treatment led to the formation of a 0.7 nm thick layer of Al2 3 nm-thick ZrO2
Ox Ny , a gate dielectric was deposited. MOSFETs were ready for As regions for
testing after subsequent annealing at 400 °C, plus the creation of a Ni/Au gate and source and drain contacts formed from a Ti/Pd/Au stack. Transistors with a 25 nm gate length produced a peak transconductance of 2.38 mS/μm at a drain-source voltage of 0.5 V. Operating at a voltage of 0.5 V for the drain (VDD
), the
device produced an on current of 0.5 mA/μm (see Figure 7) and an off- current of 100 nA/μm. Sub-threshold swing was just 72 mV/decade at a drain- source voltage of 0.1 V, rising to 77 mV/decade at 0.5 V.
Lee believes that even though the silicon industry has recently moved to three- dimensional, finFET structures, when III- Vs are introduced into the channel, there could be a move back to planar devices, such as their MOSFET. “III-V materials are vulnerable to dry-etch damages,” argues Lee, “so it might be very difficult to get fins using current dry etch techniques. In addition, planar processes could be more cost-effective.”
Devices produced by the team were designed for high-performance applications, which require an off-state leakage current below 100 nA/μm. Even lower values of 1 nA/μm and 30 pA/μm
Figure 7. The MOSFET from UCSB sets a new benchmark for on-current at short gate lengths.
must be met for standard and low-power performance, and Lee and co-workers are aiming to address these requiremnets by modifying the channel and vertical spacer.
Efforts by this team, plus those at imec and KANC, are clearly closing the gap between the state-of-the-art of the III-V MOSFET and the characteristics it requires to make an impact in the foundries. As time goes on, this gap should continue to shrink – but will it be at sufficient speed to allow compound semiconductors to make an impact at the 7 nm node?
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www.compoundsemiconductor.net Issue VI 2014 Copyright Compound Semiconductor
Volume 19 Issue 4 2013
Wafer-bonding for telco VCSELs
@compoundsemi
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Extending the life of fab tools
GaAs will fend off the CMOS threat
GaN HEMTs Ditching the package
Scrutinizing GaN HEMT interfaces
UCSB: Auger causes LED droop
News Review, News Analysis, Features, Research Review and much more. Free Weekly E News round up , go to
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