NEWS REVIEW The next graphene?
A TEAM OF ENGINEERING researchers from California has been awarded a $1.7 million grant from the US National Science Foundation (NSF) to characterise, analyse and synthesise a new class of ultra-thin film materials that could improve the performance of personal electronics, optoelectronic devices and energy conversion systems.
The potential of layering two-dimensional materials into novel heterostructures held together by weak van der Waals interactions is attracting increasing attention. Graphene has already been well studied but dozens of these one- atom- or one-molecule-thick crystals are known including monolayers of MoS2, hexagonal boron nitride, WSe2, graphane, fluorographene, mica and silicene.
Researchers at Vienna University of Technology, for instance, recently reported developing a new compound semiconductor structure combining tungsten diselenide with molybdenum disulphide to create a ‘designer’ optoelectronic material.
The Californian team is led by Alexander Balandin, University of California, who is founding chair of the materials science and engineering program at UC Riverside’s Bourns College of Engineering. (A group led by Balandin at UC Riverside previously discovered the unusually high thermal conductivity of graphene.)
Other members of the team are Roger Lake, a UC Riverside professor, Alexander Khitun, a UC Riverside research professor, and Tina Salguero, an assistant professor at the University of Georgia.
This project will investigate novel electrical, optical, and thermal phenomena in such materials and heterostructures. The research is expected to produce new material synthesis techniques and enable practical applications of ultra-thin film materials in electronic switches, optical detectors, low-power information processing and direct energy conversion. Each member of the NSF-funded team will cover different aspects of
the research and application of the van der Walls materials. Balandin will conduct materials characterization, fabrication and experimental testing of nanodevices, Lake will perform the first principal theoretical analysis and computer simulation of the properties of new materials and devices. Khitun will design circuits and systems based on two-dimensional materials and atomic heterostructures. Salguero will synthesize new materials using chemical approaches.
The NSF funding was awarded via the Emerging Frontiers in Research and Innovation (EFRI-2014) program called Two-Dimensional Atomic-layer Research and Engineering (2-DARE).
Intel patent to reduce parasitic leakage current
THE US PATENT AND TRADEMARK OFFICE (USPTO) has published a patent application filed by Intel process engineers describing a deep gate semiconductor device that uses either germanium or group III-V active layers. The idea is to reduce parasitic leakage current in small feature-size devices.
Shrinking transistor size allows more functions on a chip but it presents increasing difficulties - in particular the growing need to optimise the performance of each transistor to reduce leakage current and power consumption. Multi-gate devices, such as tri-gate transistors, have become one answer. In a tri-gate, by stacking a single gate on two vertical ones, there is more surface area for electrons to travel. In conventional processes, tri-gate transistors are generally made on bulk silicon or silicon-on-insulator substrates, which offer reduced leakage. Bulk silicon substrates are preferred as they are cheaper and tri-gate fabrication is easier, but it is often difficult to align the base of
the metal gate electrode with the source and drain extension tips at the bottom of the transistor body. Proper alignment is needed for optimal gate control and to reduce short-channel effects: if the source and drain extension tips are deeper than the gate electrode, punch- through may occur; alternately, if the gate electrode is deeper than the source and drain extension tips, the result may be an unwanted gate capacitance parasitics.
Intel’s patent application describes a solution in the form of a deep gate- all-around device, which it says is particularly suited for germanium or III-V material-based FETs with nanowire or nanoribbon channels. III-V materials are receiving a deal of interest as possible channel materials for future mainstream logic chips due to their high bulk electron mobility, which can improve the power / performance tradeoff.
Gate-all-around transistors are similar to FinFETs and Omega-FETs, which have their conducting channel wrapped
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www.compoundsemiconductor.net Issue VI 2014 Copyright Compound Semiconductor
with silicon, which forms the body of the device. The thickness of the silicon ‘wrapper’ determines the channel length. The method provides better electrical control over the channel and helps reduce leakage current. A gate-all-around differs from in that the gate material surrounds the channel region on all sides.
The device described in the patent application and illustrated above comprises: a buffer layer on a substrate; an active layer on the buffer layer; a gate electrode stack on and completely surrounding a channel region of the active layer, and also within a trench in the buffer layer; and source and drain regions positioned in the active layer and in the buffer layer either side of the gate electrode stack. The gate electrode stack is located to a depth in the buffer layer sufficiently below the source and drain regions to block a substantial portion of leakage from the source region to the drain region. The full details are described in US Patent Application 20140203327.
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