TECHNOLOGY VLSI SYMPOSIUM
team is to make a commercial impact, production of the devices will have to be transferred to 300 mm silicon substrates.
“There are a couple of options, such as wafer-bonding, a blanket approach using a metamorphic buffer, and aspect-ratio trapping,” says Shin, who reveals that the team’s preferred approach is the latter one. “We really want to use a small area on silicon, where III-Vs are defined selectively, adjacent to other devices, such as silicon CMOS and/or germanium PMOS,” says Lee. “Also, III-V materials grown by aspect-ratio trapping are known to be ideally defect-free on the top portion, enabling an overcoming of lattice mismatch issues.”
III-Vs on 300 mm silicon Leading development of aspect-ratio trapping processes for forming III-Vs on large silicon wafers is imec, a microelectronics research centre in Leuven, Belgium. At the VLSI Symposium, researchers from there unveiled the results of efforts to transfer their replacement fin process from 200 mm to 300 mm silicon.
“In the end it was a smooth transition as all the learning from the 200 mm tools for the other process steps was directly transferrable to 300 mm,” says Niamh Waldron. “Likewise, there is no fundamental issue with transferring it to 450 mm silicon.”
Fabrication of the team’s InGaAs/InP quantum-well finFETs began by taking standard shallow-trench isolation templates, and etching out the silicon to
Figure 4. Researchers at imec employ aspect-ratio-trapping technology to create III-V MOSFETs on silicon with a high-quality InGaAs channel.
form trenches (see Figure 4). Selective growth of III-Vs in the silicon-lined trenches followed. Although defects are generated due to lattice mismatch, these imperfections propagate towards the sidewalls and annihilate there, so there is relatively high material quality near the top of the trench.
Formation of the finFET fabrication began by depositing InP in the trench, smoothing the surface with chemical mechanical polishing and etching away a little InP. InGaAs was then deposited in this recess, before the surface wass smoothed again with chemical mechanical polishing, and areas beside the trench were etched away with SiCoNi to produce a protruding fin (see Figure 5).
“Controlling the damage to the III-V during etch is not a fundamental issue, but does require optimisation,” says Waldron. “We are currently working with our partners on both the replacement fin process – which does not require a fin etch – and also an etched fin approach.”
Like the team involving researchers from KANC, Waldron and co-workers used a gate-last process to temper intermixing at the interface between the channel and the dielectric.
Figure 3. The surface-channel MOSFET produced by KANC produces very high mobility, while having a low equivalent oxide thickness.
Another noteworthy aspect of imec’s approach is the use of a magnesium dopant for both the InP buffer and the InGaAs channel. Metal organics used to form these layers are carbon rich, and when carbon is present in nominally undoped InP, it leads to excessively high source-drain leakage. By introducing
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www.compoundsemiconductor.net Issue VI 2014 Copyright Compound Semiconductor
magnesium, imec’s engineers have formed p-type InP that not only slashes leakage currents, but also increases the conduction band offset with the channel layer, thereby increasing carrier confinement.
Engineers formed devices with an 30 nm-thick InGaAs channel and a 50 nm fin. For doped buffers, leakage is cut by increasing the doping in the channel – and improvements are more pronounced for lightly doped buffers. If the channel is undoped, leakage currents plummet with highly doped InP, thanks to up-diffusion of magnesium from the buffer to the channel during growth and processing. A doped channel is bad news, because carrier mobility declines. By applying conditions that offer the best compromise between leakage current and mobility,
Figure 5. A dark-field, scanning tunnelling electron microscopy image of the InGaAs channel formed by imec’s engineers. The inset is a transmission electron microscopy image of the gate stack.
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