TECHNOLOGY VLSI SYMPOSIUM
800 °C, and raised source and drain re- growth processes occurring at 600 °C. But at these elevated temperatures, gallium atoms diffuse out of the InGaAs channel, impairing interface quality and carrier transport.
The team has optimised its composite gate stack, which has a thin, passivation layer of Al2
O3 and a layer of HfO2 .
According to Shin, this pairing produces good values for the equivalent oxide thickness, and can combine with InGaAs to produce a low density of interface states.
As channel on a semi-insulating InP substrate (see Figure 1). MOCVD re-growth formed heavily doped contacts for source and drain, prior to mesa isolation, the addition of ohmic contacts for the source and drain, and atomic layer deposition of 0.7 nm of Al2 3 nm of HfO2
MOSFETs produced by the partnership were formed by first growing an In0.52 In0.7
Al0.48 Ga0.3 As barrier and a 10 nm-thick O3 and to form the gate stack (see
Figure 2). Devices were constructed with gate lengths ranging from several microns to 22 nm.
Effective electron mobility for a device with a 5 μm gate exceeded 5500 cm2 Figure 3),
V-1 s-1 at 300K (see If the technology developed by the
and with a source-drain voltage of 0.5 V, this MOSFET had excellent electrostatic integrity, including a sub-threshold swing of 80 mV/decade and a drain-induced barrier lowering of 22 mV/V.
Shrinking device dimensions led to a deterioration in electrostatic integrity. At a gate length of 40 nm, sub-threshold swing and drain-induced barrier lowering climbed to 105 mV/decade and 150 mV/V, respectively, and at 22 nm they hit 250 mV/decade and 450 mV/V.
Shin blames the deterioration in performance at shorter gate lengths on short-channel effects, which could be addressed by switching to a three- dimensional channel architecture. “When and if InGaAs is introduced into silicon foundries, it will be somewhere around the 7 nm technology node or beyond. In those regimes, the transistor architecture should be non-planar, such as a three- dimensional channel or gate-all-around, to guarantee electrostatic integrity.”
Figure 2. Cross-sectional transmission electron microscopy images of structures produced by the team led by researchers from KANC. These images show the photoresist, HSQ, and the dummy gate, for gate lengths of 1 µm (a) and 22 nm (b). High-resolution images offer insights into the quality of the interface between the In0.3 (c), and the Al2
Ga0.7 O3 quantum well. /HfO2
As channel and the regrown GaAs gate stack on the InGaAs/InAlAs
Copyright Compound Semiconductor Issue VI 2014
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