Industry: SiC power electronics
drivers with our SiC SJTs because their continuous gate current requirement can be supplied by such ICs. The magnitude of this current can be controlled with a series gate resistance, similar to that used in an IGBT drive, and its addition can also provide the requisite gate-source voltage (3-4 V) for operating this class of junction transistor.
One option for driving all these switches is to combine a commercial gate driver IC with an isolated input signal and a resistor-capacitor output network (see Figure 2). Using this approach, our SJTs can be driven with gate voltages as low as 8–10 V. One additional benefit of using this particular type of SiC switch is that it does not require a negative gate voltage to remain off.
Due to the high voltages being switched, the input signal source from potential high drain voltages needs to be protected with an optocoupler or isolator. The isolation rating of this component should greatly exceed the predicted DC voltages in use, particularly with an inductive load present. Choke coils can also be inserted if common-mode noise in the circuit on voltage supplies and gate driver inputs and outputs is too high.
Dynamic considerations These gate drive considerations only take into account steady state, on-state operation, and it is much more important to consider dynamic losses at high operating frequencies. This is because SiC switches lead to the biggest gains in efficiency over the silicon incumbents when they operate at tens or hundreds of kilohertz. Operating in this regime, the losses associated with the driver and the entire system are dominated by charging and discharging of the gate-source and the Miller capacitances (the capacitances seen looking into the input).
Driver switching losses are directly proportional to the product of the gate-source (CGS
) capacitance
and the square of the voltage swing. This swing is typically 4-5 V for SJTs and normally-off JFETs, but it can be as high as 20-30 V for MOSFETs
) capacitance and the square of the device voltage swing, which could be as high as 800 V. Today, the value of CGD
and normally-on JFETs – implying that dynamic capacitive losses in the latter devices can be up to 50 times higher. Meanwhile, the device switching loss is governed by the gate-drain (CGD, Miller
can be two-to-three times
lower for SJTs and normally-off JFETs, compared with a MOSFET of a similar current rating. So, in summary, SJTs and normally-off JFETs are significantly ahead of their SiC rivals, when it comes to efficient operation in driver circuits.
We have assessed the switching performance of our SJT in the gate drive circuit outlined in Figure 2 using an industry standard, double-pulse switching test. Measurements reveal a current rise time, tr
, of only 16 ns, and a fall time, tf , of 26
ns (voltage and current waveforms of the SJT are shown in Figure 3). Total device switching energy loss is only 97 µJ per cycle, equating to less than 10 W of device switching loss at 100 kHz, while switching 600 V/6 A (3.6 kW).
Lower losses are possible by turning to a parallel resistor and capacitor on the gate driver IC output, similar to that used in high frequency IGBT drivers. With this change, a dynamic gate current waveform is introduced – due to the presence of a transient gate current peak from the charging of the gate capacitor – and this turns the SJT on and off more quickly (see Figure 5 for an example).
Figure 5: The waveform of the transient gate current, IG
, while driving a 1200 V / 6 A SJT. Similar gate current switching transients are observed in MOSFET and IGBTs as well
It is possible to alter the static and dynamic performance of the SJT – and to ultimately trade-off the switching speed to the device and the driver losses to fit the particular application demands – by adjusting the gate resistor, capacitor, and gate driver output voltage. For a fixed driver output voltage, higher capacitance leads to higher current peaks (see Figure 6(a)) with shorter rise and fall times (see Figure 6 (b)). However, increasing capacitance can have its downsides, such as higher device and driver losses (see Figures 6 (c)). So it is important to hit a sweet spot, where the gate capacitance is low enough to trim device and driver losses but still high enough to obtain desired switching speeds. Care must also be taken to avoid ringing, which may occur in the gate drive output network due to interplay between the gate capacitance and the
Figure 4: An industry standard, double- pulse switching test demonstrates GeneSiC’s SJT switching performance using the gate drive circuit detailed in Figure 2. During testing, the SJT is turned on with the application of a gate current IG current ID
and the drain is ramped up
linearly while flowing through the inductor and SJT in series until ID
hits
6 A. At that point the SJT is switched off, and then switched back on after a 2 µs delay to record device turn-on
In industrial applications, higher efficiencies are being reached through greater deployment of fast, power-semiconductor switches in variable speed drive motors
July 2013
www.compoundsemiconductor.net 43
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