INDUSTRY PHOTONIC INTEGRATION
scale. This involves placing ‘chiplets’ of custom unprocessed InP epitaxial material on the silicon photonic circuit. Using standard semiconductor lithography and etch steps, InP-based chiplets are processed in parallel to form lasers, optical amplifiers, modulators and photodetector devices. In every case, they are registered to the underlying waveguides and optically connected through evanescent mode converters, which provide a conduit between the silicon and InP layers for the optical mode propagating through the circuit.
Figure 2. Heterogeneous integration process flow: 1) InP chiplets are bonded to the pre-defined silicon photonic circuit, 2) the chiplets are thinned to reduce wafer topology, 3) photolithography and etch steps are performed to define the InP device structures and align them to the underlying silicon waveguides, and 4) dielectric deposition, metal deposition and etch steps are performed to form contacts for electrical inputs
California, Santa Barbara, has shown that it is possible to overcome these issues by turning to a radically different architecture – one that uses silicon to define a laser’s cavity, while using III-V materials to provide efficient gain.
Commercialising hetero-integration At Aurrion of Goleta, CA, we have developed a heterogeneous platform for integrating InP-based semiconductor materials onto existing silicon photonic substrates. This enables all photonic functions, including the laser, to be brought together onto a single chip. The basic underlying photonic circuit, comprised of low-loss silicon and dielectric waveguides, is generated on a silicon- on-insulator substrate using established foundry infrastructure. Thanks to this approach, cost advantages result from: the leveraging of shared resources; the use of 8-inch substrates, rather than 2-inch substrates, the common platform for photonics; and superior yield, which stems from higher-capacity foundries with greater capability and better quality systems, compared with traditional III-V photonics fabrication facilities.
Our process features a bonding step to add InP functionality to the photonic circuits at the wafer-
to the photonic circuits at the wafer-scale. This involves placing ‘chiplets’ of custom unprocessed InP epitaxial material to the silicon photonic circuit. Using standard semiconductor lithography and etch steps, InP-based chiplets are processed in parallel to form lasers, optical amplifiers, modulators and photodetector devices
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Once that has been carried out, further processing steps encapsulate InP with dielectric materials, and also form metal interconnects and contacts for driver and control circuitry. Finally, the chip is housed in a package, using technologies developed for the electronics industry. By being able to take advantage of the developments in that mature sector, we are able to use 2.5D or 3D interposer technologies to tightly integrate our photonic chip with advanced node electronic driver chips.
One of the attractive features of heterogeneous integration is that it allows a wide choice of gain materials, which do not have to be placed on the silicon chip with a tremendous degree of accuracy. Thanks to this, it is possible to process photonic circuits operating in disparate wavelength regimes side-by-side on the same chip. We have recently demonstrated this capability to deliver photonic laser sources for telecom and datacom applications united on a single wafer (more details can be found in B. R. Koch et. al. “Integrated Silicon Photonic Laser Sources for Telecom and Datacom,” in Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2013, OSA Technical Digest (Optical Society of America, 2013), paper PDP5C.8).
What’s more, our capability to integrate multiple, tailored InP quantum well epitaxial materials throughout the photonic circuit provides us with a silicon integration platform that permits the unique realisation of high performance InP-based active
Our process features a bonding step to add InP functionality
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