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technology  SiC electronics


product. But this device has been incredibly useful, providing an important building block for the fabrication of our 2.2 kW SIT. It has enabled us to establish our design rules, such as transistor channel width and length. These critical design rules have been subsequently validated by hooking up real devices with probes and extracting their electrical parameters. Devices that we have created adhere to these rules, indicating optimization of the fabrication processes and unit cell RF power performance.


To realize the high output powers demanded by applications such as pulsed radar, we have had to significantly up-scale the transistor cell size. Scaling is not trivial, because increasing chip power density does not necessarily result in amplifier output power scaling. That’s because thermal issues can hamper performance, which are related to the extremely high output powers produced by the chip.


Figure 2. AFM images of Microsemi’s SiC epiwafers indicate their low level of surface


roughness


guided wafer fab process improvements. Thanks to all this effort we have established sources of material that are prepared to supply our volume production requirements for the next 10 years and beyond.


Within our 4-inch silicon power chip fab in Bend, Oregon, we have created a completely self-contained wafer manufacturing capability. The processes established at this facility include heated implants at up to 1000 °C and implant annealing at up to 1700 °C.


All the tools in this fab that are used for SiC device production are capable of processing both 3-inch and 4- inch SiC. Today all our manufacturing is carried out on the smaller of these sizes, but over the next two years we plan to migrate to the larger format. Our installed 3-inch wafer capacity is capable of supplying all projected radar programs over the next several years. Switching to 4-inch production will more than triple our capacity, and also increase tool redundancy.


Scaling-up


Our first prototype transistor cell produced only a fraction of the 2kW output power that’s possible with our latest


Figure 3. Source pull (left) and load pull (right) analysis offers a quick way to determine the optimum input and output device


impedance over the band of interest


32 www.compoundsemiconductor.net August / September 2010


However, by optimizing chip geometry we have been able to scale the device without any loss in performance. This has been realized by first performing experiments with design factors such as transistor cell size, chip geometry and chip thickness. Evaluating these results has enabled us to build devices that produce output powers approaching the theoretical transistor periphery-scaling factor.


All the customers that we are targeting with our 2kW transistors demand operational lifetimes in excess of 30 years. To meet this requirement we house our SIT in a hermetically sealed package, use gold-wiring throughout, and employ package plating and a gold-tin seal. History is on our side, because this approach has a proven reliability, having already served successfully in many highly demanding applications. However, due to the substantial increase in overall RF power and power dissipation, a new design is being implemented. This includes qualification of multiple suppliers. Our 2 kW device realizes such a high output power by combining several high-power transistor, multi-cell chips. To ensure the highest levels of repeatability and consistency in RF


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