technology GaN power devices
Figure 2: The wafer bow in the 150 mm, GaN-on-silicon epiwafers is well below 60 µm, the upper limit for high-volume processing
need new material technologies, such as gallium nitride. Turning to this wide bandgap semiconductor is very attractive because it also enables a 50 to 90 percent reduction in both the size and the weight of conversion subsystems, thanks to a massive cut in cooling system requirements.
Although the first GaN HEMT transistor was invented more than 15 years ago by Asif Khan, significant development efforts on practical power devices employing GaN-on-silicon technology are fairly recent. Tremendous progress in this technology is expected over the next 10- 20 years, and in just five years figures of merit could improve by an order of magnitude.
silicon-based IGBT, which combines the ease of charge control with the benefits of conductivity modulated drift resistivity. This is often selected for lower frequency conversion systems such as motor drivers.
Significant engineering efforts over the last three decades have driven substantial progress in the performance of both of these devices – figures of merit have improved by an order of magnitude. But wringing out any further gains in performance is going to be tough and costly. It is likely that efforts could yield an economically feasible factor-of- two improvement in the 30 V FET, and a five-fold gain in 600 – 1200 V silicon IGBTs. But any further advances in power device performance for future electronic loads will
Despite all this promise, GaN devices are generally failing to fulfill their commercial potential. That’s because they are too expensive to produce, due to the costs associated with substrates, epitaxy, device fabrication, packaging, support electronics and development. The power device marketplace has set a viable, economic-based limit of about $ 3/cm2 for substrate and epitaxy costs, restricting the choice of substrates to just silicon. Multi-wafer MOCVD tools are essential for providing the required throughput and an acceptable cost-of-ownership, although their current status is quite primitive compared to modern silicon processing equipment.
In addition to realizing low costs for substrates and epitaxial layers, it is imperative to minimize device fabrication costs. To do this, manufacture should employ substrates at least 150 mm in diameter. Selecting such platforms has an additional, significant benefit - widespread availability.
Fabrication of compound semiconductor devices often involves specialized processes such as e-beam and lift-off lithography, and may also include gold metallization steps. Products for military and RF applications can justify the inclusion of these expensive techniques, because the market is willing to accept costs of more than $ 10,000 for finished 100 mm wafers for discrete devices. But these manufacturing costs are incompatible with the far broader power device market.
Figure 3: A proprietary insulated gate reduces the reverse-bias drain-leakage current in IR’s GaNpowIR devices with a gate length of 0.3 µm. The HEMTs, which have gate-source and gate-drain spacings of 1 µm, exhibit a punchthrough-limited, source-drain breakdown of more than 40 V for a gate voltage of -20V
28
www.compoundsemiconductor.net August / September 2010
If power devices based on wide bandgap materials are to displace the incumbents, they must have comparable fabrication costs. Realizing this is only possible by manufacturing devices in volumes comparable to that of silicon devices. In other words, a production throughput of at least 10,000 wafers every week. These volumes must be produced with high yields, using silicon-compatible semiconductor fabrication lines, taking advantage of the current high volume of silicon demand. If these goals are fulfilled, it is possible to tap into today’s broad market for power devices that equates to 10 million, 150 mm wafers per year. Success requires significant scalability in device
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