IEDM  conference report


GaN HEMTs: faster, more capable and better understood


Low-resistance channel contacts that speed transistors to record-breaking frequencies, localized boron-doping that boosts blocking voltages and studies of HEMT ageing mechanisms all featured at the latest International Electron Devices Meeting. Richard Stevenson reports.


A


dvances in silicon technology have dominated the agenda at the International


Electronic Devices Meeting (IEDM) for more than fifty years. However, recently this meeting has also featured a handful of presentations on GaN HEMTs, showcasing the progress made with this device. According to papers at the most recent meeting, not only is this class of transistor operating at far faster speeds than ever before and blocking higher voltages – a more detailed understanding of why it fails is coming to light, and superior models are being developed to aid the building of circuits based on these HEMTs.


One of the highlights from the latest IEDM, which was held in San Francisco from 6-8 December 2010, was a paper from a team from HRL Laboratories claiming the record for the fastest GaN HEMTs. These transistors, which have gate lengths as short as 40 nm, produce a peak cut-off frequency of 220 GHz and a maximum oscillation frequency of 400 GHz. The record-breaking results are believed to stem from an impressive set of DC characteristics: on-resistance is just 0.81 Ω.mm; drain current hits 1.61 A/mm; off-state breakdown voltage is 42 V; and extrinsic transconductance peaks at 723 mS/mm, reducing the contribution from parasitic capacitances.


HRL’s HEMTs employ a barrier made from AlN. This wide bandgap material has the benefit of producing strong polarization effects, but it also creates a high potential barrier for electrons, making it difficult to form a low- resistance ohmic contact to the channel. The issue is addressed by re-growth of heavily doped GaN contacts by MBE, according to West-coast team. They have fabricated double-heterostructure HEMT epistructures by MBE on 3-inch SiC. An Al0.08


Ga0.92 N layer was deposited


first, followed by a 20 nm-thick GaN channel and then a top barrier comprising 3.5 nm of AlN and 2.5 nm of GaN (see Figure 1). The thin top barrier cuts gate-to-channel- distance while maintaining a high two-dimensional electron gas density and a low gate-leakage current.


The HRL team produced transistors with gate lengths ranging from 40 nm to 200 nm. Chlorine-based reactive ion etching exposed part of the channel, before MBE added 50 nm-thick GaN layers with a silicon doping level of 7 x 1019


cm-3 . These formed the basis for source and


drain electrodes that were created by adding titanium and platinum. A tri-layer electron-beam technique created T-shaped gates made from platinum and gold, before these devices were passivated with 50 nm of SiN.


Cutting gate length from 200 nm to 40 nm increased transconductance from 672 mS/mm to 723 mS/mm and reduced threshold voltage by 0.5 V, indicating that gate scaling was not impeded by short channel effects. Measurements of the cut-off frequency at a range of gate lengths confirmed this and indicated that miniaturization reduced parasitic delay. Modeling showed parasitic charging time accounted for one-tenth of the total delay time for 40 nm transistors with a source-drain voltage of 2 V. The gate transit time scales with gate length, which is another promising sign that further reductions in device size should increase the speed of these transistors.


January / February 2011 www.compoundsemiconductor.net 21


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