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In order to become a successor to silicon CMOS technology, III-V transistors must be built on silicon substrates that are large enough to be processed by VLSI toolsets. Sematech has done just this by fabricating InGaAs MOSFETs on 200 mm silicon (100) using state-of-the-art silicon foundry tools. Richard Stevenson investigates.


Sematech builds III-V transistors on large silicon wafers


B


ack in the twentieth century, the route to making faster, cheaper silicon chips was clear-cut: simply reduce the size of the transistor. But if such an approach had been adopted in recent years, it would have failed to deliver the gains in performance needed to keep pace with Moore’s Law.


To maintain the level of progress prescribed by that Law, foundries have modified the standard silicon MOSFET and introducing new, more exotic materials. One of these is HfO2 SiO2


increase in leakage current with transistor scaling. Another change is the introduction of silicon germanium, which is used to strain the pMOS device and speed the passage of holes from source to drain.


The trend of incorporating a wider palette of materials is set to continue – the International Technology Roadmap for Semiconductors is advocating a move away from silicon transistors from 2015, when the 11 nm node will be rolled out. III-V MOSFETs are widely viewed as the most likely successors. However, despite their rich, long history of development, there is still a great deal to do before compound semiconductor transistors can be churned out in their millions at the world’s leading foundries.


Development of III-V MOSFETs dates back to the 1960s. Then, just like now, the appeal of turning to this class of material stems from its very high electron mobility, which promises to lead to far faster chips. Finding a gate material that forms a high-quality interface with compound semiconductors has been one of the biggest obstacles to realizing such a device. SiO2


favor of other silicon compounds, sulfur passivation techniques, gates made from Ga2


and Gd2 O3


was quickly discarded in O3


oxides,


and more recently, atomic layer deposition of aluminum oxides. There has also been a switch from a GaAs channel to an InGaAs one that sports superior transport properties.


Nearly all of this work has involved a native substrate for III-V transistor development – reports of device fabrication


on silicon substrates, the only material platform enabling a practical successor to silicon CMOS, have been few and far between. And almost all these efforts have used silicon substrates that are far too small to be processed by leading silicon foundries equipped with state of the art toolsets.


, which is used as the gate material. This replaces , a dielectric that would now lead to unacceptable


The one exception is an effort by Sematech, a US-based nonprofit consortium of major semiconductor and chip- manufacturing equipment makers that performs basic research on chipmaking. At the recent International Electron Devices Meeting, Sematech front-end process device engineer Richard Hill detailed the fabrication processes and device results of In0.53


Ga0.47 As MOSFETs


with varying gate lengths that were formed on 200 mm silicon wafers using state-of the-art manufacturing tools.


“Our devices have been manufactured using a VLSI toolset, with processes that could be carried out in any one of the big foundries or IDMs,” says Hill. Turning to VLSI enables the fabrication of chips with very high levels of integration and a very small pitch, attributes that are impossible to realize using traditional III-V transistor manufacturing methods.


Figure 1. The spread of threshold voltage in the III-V transistors made by Sematech is comparable to that of a batch of silicon devices, and far tighter than that produced in University labs


January / February 2011 www.compoundsemiconductor.net 13


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