technology research
CMOS integration, which will require a far thinner buffer. On top of the buffer sits a 16 nm-thick In0.53
Ga0.47 Al0.47 O3
As, and an In0.53 and ZrO2
Ga0.47 As
channel, a 4 nm-thick spacer and a 8 nm-thick barrier that are both made of In0.53 that is 3 nm thick. An Al2
As cap gate is added,
before silicon is implanted into the channel and source and drain contacts formed to yield a surface-channel MOSFET (see figure 3).
“It’s a three terminal device, not a standard bulk MOSFET,” says Hill, who compares it to a silicon-on- insulator MOSFET. One of the strengths of the Sematech device is that its InAlAs buffer has a wider bandgap than the InGaAs layer, which ensures decoupling of the channel from the underlying layers. This leads to immunity from short channel effects, which inhibit channel control by the gate and can include an increase in off-state leakage with increasing drain current and higher junction leakage. Short channel effects can prevent the transistor from being turned off as it is scaled to smaller and smaller dimensions.
The MOSFETs produced by Sematech have gate lengths varying from 20 µm to 0.5 µm. The shortest variants have a drive current of 471 µA/µm, a transconductance of 1005 µS/mm and an electron mobility of 1000 cm2 a sheet doping of 1 x 1013
/Vs at cm-2 . These devices do have
one cause for concern, however – a leaky buffer. Measurements between isolated mesa structures indicate that buffer resistance is about 14 kΩ/, which is more than four orders of magnitude lower than that for typical metamorphic InAlAs buffers deposited on GaAs substrates. Transmission electron microscopy and atomic force microscopy measurements on the MOSFETs indicate that the buffer is riddled with defects. Their density in this layer is 109
cm-2 , a value high enough to
account for the high leakage current in the buffer (see Figure 4).
“You can conclude the leakage is going through the buffer for two reasons,” explains Hill. “The off-current does not scale with temperature, so it is not an interface state density problem; and the off-current does not really scale with gate length, so we know it is a very deep leakage.”
Device on-performance is not hampered by the high defect density. According to Hill, that’s because electron mobility is not governed by the mobility of the two- dimensional electron gas, which is limited by phonon scattering: “It’s actually [determined] by the surface roughness and interface roughness scattering at the oxide-semiconductor interface.”
The road ahead
Efforts at improving the buffer are on going. Very recently Semtech’s engineers slashed the defect density in this layer, which should drive down the transistor’s leakage current. One of the next goals is to thin the buffer to 0.5 µm or less, a step that must be taken to enable this layer to be used in a successor to silicon CMOS. To realize this, Sematech’s engineers are looking at alternative material technologies, such as MOCVD
growth, selective growth rather than blanket growth, and aspect ratio trapping. Investigating other types of transistor structures is also on the agenda. The type of MOSFET used by Sematech’s engineers up until now was partly chosen because it can be fabricated using a process flow that is very similar to that used to produce silicon transistors. Now the team wants to look at processes for making various types of MOSHEMTs, including those with a recessed gate.
“There are many advantages and disadvantages of each technique, and it is not clear to us at this point which one is going to be the winner,” says Hill. “One of our next steps is to build flows with all these different device types and compare them at gate lengths that are similar to where the silicon industry is right now.”
In addition to scaling buffer thickness and gate length, Sematech’s engineers will try to reduce contact resistance and junction resistance, and improve the gate stack. It is possible that they will complement this effort with this electron transport device with one based on hole transport, because both types of transistor are needed to build a silicon CMOS successor. “There has been some work published on antimonides with mobilities of about 1000 cm2
/Vs, and in some ways an all III-V solution may
be advantageous from an integration strategy,” muses Hill. “But germanium technology is more mature.”
If all this effort is to lead to III-V MOSFET production in silicon foundries in four or so years time, solving of technical goals must go hand in hand with manufacturing technology developments. According to Hill, it will take a couple of years to order tools, install them and ramp up manufacturing. “That infrastructure development has to be started now to get on the correct time scales.” Hopefully the toolmakers will hear this rallying call, act on it and help III-Vs to play a key role in extending Moore’s Law.
© 2011 Angel Business Communications. Permission required.
January / February 2011
www.compoundsemiconductor.net 15
Figure 4 Transmission electron microscopy image of the cross-section of hetero-buffer. GaAs areal defect density was estimated to be ~1x109 cm-2
. The
defectivity of the metamorphic buffer is
significantly higher
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