August, 2019 Continued from previous page


data busses to write to the memory and then read it back. This is done by placing the JTAG device to which the memory is connected into boundary scan mode and using that to manipulate the individual lines of the bus to mimic the read and write cycles normally used on the interface. In this way, test patterns are applied to the address and data busses and the memory’s control pins. Careful design of these test patterns makes it


possible not only to detect an assembly defect, but also to identify the affected net. This test method is slower than using the built-in connectivity test features of DDR4 and GDDR5/6 memories because of the repeated memory read/write cycles required, but achieves identical test coverage.


Retention Time and Refresh The memory’s data retention time is relevant


when discussing the use of boundary scan for DDR memory because the internal refresh cycles are not happen- ing. The JEDEC standard specifies that DDR parts must have a retention time of at least 64 ms across its oper- ating temperature range. Writing a word into memory


using boundary scan often requires twenty complete scans, and as it can typically take between 0.2 and 2 ms to perform one scan, we see that each write cycle generally requires 4 to 40 ms. A complete test can therefore exceed 64 ms. However, devices in practice have retention times far in excess of that specification limit, and studies have shown that even the leakiest cells have data retention of over a second at room temperature — perfectly sufficient for boundary scan requirements.


High-Speed Testing In comparison to the speed at


which DDR runs, boundary scan test- ing can be considered DC. This has an advantage in that it can detect micro- cracks in the solder joints that high- speed tests may miss due to capacitive effects enabling a high-frequency sig- nal to pass where DC cannot. Such cracks can lead to early-life failures when they experience thermal expan- sion/contraction and oxidation. As well as running a boundary


scan, however, it can be beneficial to perform a high-speed test because signals may behave differently when running at MHz rates. A simple way to achieve this is to load test firmware into the processor or FPGA


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that interfaces to the memory to allow it to per- form the write/read cycles directly, rather than going through boundary scan registers. Test pat- terns will now be loaded and read at high speed over the normal busses, executing a high-speed test. The disadvantage of this is the need to write processor-specific software, whereas the boundary scan test has no such requirement. Although DDR4 DIMMs may be built from


memories that have ten control inputs, those signals are not routed to the connector. When performing automated tests on assemblies using DIMMs, the DDR4 connectivity test mode cannot be used. In that instance, it is necessary to use standard boundary scan test methods, such as those described for DDR3. We have seen that the current generation of


memory devices, such as DDR4 and GDDR6, incor- porate internal circuitry that provides fast and efficient methods to confirm the part has been cor-


rectly placed on the board, that it is functioning, and has no soldering defects such as open-circuit, short-circuit or “stuck-at” faults. These connectivity test modes have led to a


reduction in the time taken to check the devices because there is no longer a need to write and read to the memory cells during testing. When designing a board that incorporates memories with an inter- nal test capability, it is strongly recommended that Test/Scan Enable and other control signals are rout- ed to the I/O pins of a JTAG-enabled component or to a test header. By doing so, the designer enables the use of automated connectivity testing that can save many hours of debug time on first prototypes, as well as during mass production. Contact: XJTAG, St. John’s Innovation


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