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August, 2019


DDR Memory Connectivity Testing and Boundary Scan


By Stephen Love, CTO, XJTAG


BGA packages, ways to verify error- free assembly become ever more important. One option is boundary scan testing, which offers an automat- ed method to check components are operational, correctly placed, and free from soldering faults, without the need to run any software on the board.


W When JEDEC published stan-


dards for GDDR5 and DDR4 memo- ries, they defined inbuilt test features that work with these systems to sup- port rapid checking for assembly faults. Such methods can prevent many wasted hours by providing early detection of problems, and are as applicable to the first prototype boards as they are to mainline production. The drive to support this style of


in-circuit testing has continued into the latest GDDR6 specification, pub- lished at the end of 2018. Connectivity test methods are available for these memory devices, and similar checks can be performed on LPDDR4 and DDR3 components, which do not incorporate inbuilt test modes.


DDR4 Co Larger DDR4 memories include


a test feature that can be used to check the connectivity of their pins. When the Test Enable (TEN) input is assert-


Figure 1: DDR4 connectivity testing. By applying a series of different


test patterns and reading the result- ant outputs, it is possible to confirm that the non-power pins are free from open-circuit, short-circuit or “stuck- at” faults. If a defect is found, a care- ful choice of input patterns even allows the fault to be pinpointed to a specific net. The advantage of this method is


6/17/19 1:07 PM Page 1


that the test is performed without the need to write or read the memory


cation to apply these test sequences and to monitor the resulting outputs is to use boundary scan techniques. This rarely requires any changes to the circuit board. In most designs, the DDR4 balls are already routed to a processor or FPGA that probably has boundary scan capability. To initiate a connectivity test, a


PC connected over the JTAG port places the processor or FPGA into JTAG test mode. This isolates its


ith the complexity of electron- ic circuits continually grow- ing and the increased use of


ed, the memory cells become bypassed and the pins’ functionality changes. Many become inputs, which an inter- nal asynchronous logic tree combines to produce outputs on other pins.


cells themselves, making it a fast process.


Gaining Access with JTAG The simplest way for a PC appli-


non-power pins from their normal functionality and instead connects them internally to a boundary scan register. This gives the PC control of the nets connected to those pins as shown in Figure 1. In this way, PC- based software can control the mem- ory’s TEN pin and apply the required test vectors. The resulting outputs are read


back into the register and then clocked serially out of the board’s JTAG port for the PC software to analyze. This is all done without the need for any soft- ware to run on the board and is there- fore suitable for early prototypes before any code has been written. All the low-level control is performed automatically by PC software that uses imported BOMs and netlists to make the process simple.


Practical Limitations While this test mode was a wel-


come addition to the DDR specifica- tion, its approach of fixing which pins are inputs and which are outputs does


impose limitations. For


instance, the memory’s DQS_t and DQS_c lines are used as two separate outputs in test mode. However, because they form a differential pair in normal use, the JTAG device’s pins they connect to are often fixed in differential mode and therefore can- not be read as two independent logic


Continued on next page


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