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DDR Memory Connectivity Testing and Boundary Scan


Continued from page 55


Figure 2: GNNR6 boundary scan.


using the board’s test connector. This test method imposes fewer


restrictions than the DDR4 imple- mentation because the four pins used to control the scan function are mul- tiplexed onto signals that are defined as standard logic inputs in normal use (Scan Enable, Reset, Chip Select, and Mirror Function). It must be noted, though, that a circuit designer should not tie Scan Enable or Mirror Function solely to fixed voltages (a temptation for normal use) but should route them to pins of a JTAG device so that it can override their default state when in boundary scan mode.


GDDR6 Boundary Scan Test Mode


ELECTRONIC ASSEMBLY GmbH · sales@lcd-module.com · www.lcd-module.com The GDDR6 standard brought


 


IEEE 1149.1 compatible boundary scan to these devices. Unlike GDDR5, test patterns are not loaded by the data bus, but are serially clocked through the boundary scan registers using JTAG. The two mem- ory channels have their own regis- ters, with their individual data paths connected sequentially as shown in Figure 2. As with all boundary scan tech-


niques, when the memory is placed into test mode, its balls become iso- lated from their normal functionality and, instead, connect to the bound- ary scan registers shown in the dia- gram. A series of carefully selected test vectors are clocked into these registers with a JTAG connection, and the resulting states of the mem- ory’s pins plus those of other devices that can be accessed via JTAG are checked to ensure they are as expect- ed. In this way, it is again possible to check for assembly faults on the memory connections, and to identify the affected net. With GDDR6, it is not neces-


               


Manufactured in the U.S.A. since 1966 www.westbond.com


1551 S. Harris Court Anaheim, CA 92806 Tel 714·978·1551


sary to interface by using a JTAG device, but the JTAG can interface directly to the memory. Being a true boundary scan device, it can also be used to sample the state of all the nets it connects to, thereby checking continuity from other devices on the board. Due to its compatibility with IEEE 1149.1, a chain can be estab- lished that incorporates the board’s processor or FPGA, the GDDR6 memory and any other JTAG- enabled components, simplifying testing of the complete board.


Testing LPDDR4 and DDR3 The method for testing devices


such as LPDDR4 or DDR3 that do not have an inbuilt test feature entails exercising the address and


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