August, 2019


A Shortage We Can’t Afford...


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or impending loss, of manufacturers or suppliers of items, software and raw materials. Compliance to guide- lines found in SD-22 are apparently voluntary. Under what circumstances


would the Federal Government inter- vene and force FPGA makers, who are currently reliant on the services of a sole-source subcontractor, to broaden their vendor base? Has a disruption in the FPGA


delivery cycle ever happened? The unthinkable actually occurred not too long ago. The principal inventor of solder columns, IBM, sent shock- waves across the aerospace and defense industries after announcing their intention to exit ceramic col- umn grid array (CCGA) FPGA pro- duction in 2013. After shutting down, IBM sold (licensed) their column packaging technology to Silicon Turnkey Solutions (STS), now owned by Micross. During the aftermath, IBM’s entire CCGA production line was boxed up and sat in storage in crates for three years before being put back into service. Xilinx had depended on IBM to


package Xilinx’s flip chip FPGA product line. It took more than a year for Xilinx to retool and qualify its FPGA product line with other suppli- ers. During the changeover, Xilinx selected a sole source supplier of sol- der columns to replace IBM. Is Xilinx’s product line still at risk of disruption should their current sole- source subcontractor stop delivering column attachment services on rad- hard FPGA packages? Copper-wrapped solder columns


are constructed primarily of three materials — a high melting tempera- ture solder core, such as Pb80/Sn20, wrapped with a thin ribbon of pure copper wire, all coated by eutectic Sn63/Pb37. The combination of these three materials comprising a solder column relieves stress caused by the mismatch of the coefficient of ther- mal expansion (CTE) between a ceramic FPGA package and an FR4 PCB. To enhance reliability for mis- sion-critical applications, alternative interconnects, such as solder balls, cannot be used on large ceramic FPGA packages. Dependence upon a sole-source


subcontractor with a monopoly on attaching copper-wrapped solder columns is tempting fate and asking for trouble. This is particularly true in light of the reality that the loss of that source, for any reason, could quickly mean a catastrophe, domino- style, for a host of defense- and aero- space-related industries, and even national security itself. It would be wise for the U.S. Department of Defense (DoD) to expedite the quali- fication of multiple subcontractors of vital FPGA services, since these devices are so critical to the welfare of our national security. Contact: TopLine Corp., 95


Highway 22 W., Milledgeville, GA 31061 % 800-776-9888 fax: 478-451-3000 E-mail: sales@topline.tv Web: www.topline.tv r


See at NEPCON Asia, Booth 1J55


www.us- tech.com


DDR Memory Connectivity Testing and Boundary Scan


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inputs, even in boundary scan mode. This restriction, and the fact the fea- ture is not mandatory on lower capacity DDR4 devices, has caused some users to be disappointed with this test mode. However we can look forward to seeing how it has been updated in JEDEC’s long-awaited DDR5 specification.


GDDR5 Scan Test Mode While GDDR5 (Graphics DDR,


not DDR5) also includes a method for checking connectivity, it is different to that adopted in DDR4, because it does


not use internal logic to combine inputs. When its Scan Enable (SEN) pin is asserted, its non-power pins are isolated from their normal functional- ity and are instead connected to an internal boundary scan register. Test patterns are sent to that


register over the device’s parallel data bus and are applied to its pins. The actual states of those balls are then captured and serially clocked out of the memory’s “Scan Out” pin. At the same time, the JTAG device it connects to scans the other end of the tracks. Any differences between the sent pattern, the one read back, and


what is seen at the JTAG device’s end identify any connectivity errors. Repeating this with different pat- terns checks all the non-power pins. As with DDR4, the memory chip


is controlled for the duration of this test by the JTAG-enabled device to which it already interfaces. That device is placed into boundary scan mode, and the relevant bits of its boundary scan register become the control for the memory, the connec- tion to the bus, and the input for the Scan Out data. Information is passed between the JTAG device and the PC


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