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March, 2015


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Boundary-Scan Testing Checks Complex Circuit Designs Continued from previous page


extreme that may not occur at room temperature. Delays can be added by lengthy repair times, due to support departments with poor test capabili- ties.


The Life Cycle Aspect Boundary-scan methods can


help resolve many of the manufactur- ing delay issues, bringing quality improvements with economic bene- fits. Boundary-scan technology is par- ticularly effective if it is implemented on a corporate basis as a fundamental part of a firm’s test strategy. Boundary-scan tools can help


achieve design-for-testability (DFT) goals. Using these tools early in the product cycle can result in reduced time-to-market and improved prod- uct quality. A designer will know, prior to


prototyping, the level of test coverage possible for the product. If the test coverage is inadequate, the design can be modified and the test coverage reevaluated, avoiding the delays that would result from subsequent addi- tional process steps caused by inade- quate testing. By adopting a policy in which the design phase must include DFT analysis that meets coverage requirements, an organization can avoid wasted layout spins and unnec- essary prototype builds. Boundary-scan tools can help


test prototypes more efficiently. Unlike structural test methods such as in-circuit testing, boundary-scan testing requires minimal test fixtur- ing. As a result, boundary-scan meth- ods can be applied to small prototype runs for detection and rapid repair of structural faults. Screening for structural faults


enables the designer to properly focus on design issues during the critical prototype stage. Boun dary-scan meth- ods can even provide access to a large set of test points for electrical stimu- lus and sensing during the debug process, as well as a convenient


Boundary-scan testing identifies manufacturing


faults typically caused by soldering problems, while functional testing is


suitable for at-speed prob- lems, such as faults that are manifested at


operating range limits, user-generated errors, etc.


means of rapidly programming (and re-programming) flash and logic cir- cuit elements on a board during firmware verification. The ease of applying boundary-scan methods means that design revisions can be quickly incorporated in the test and programming routines. Boundary- scan tools can optimize structural testing and improve production test efficiency in several important ways. Boundary-scan-based tests typi-


cally run at high speed (on the order of tens of seconds even for complex PCBs) and can yield pin-point diag- nostics, allowing the simplification or elimination of fixturing for testing. The modular nature of boundary- scan methods allow them to be com- bined with many other structural test methods, such as in-circuit test-


See at NEPCON China, Booth B-1C20


ing or flying probe testing, which may already be in use in the factory.


Trapping Defective PCBAs Circuit boards with faults not


detected by structural testing are said to “escape” to the functional test stage. These “escape” boards may be detected during functional testing but, at this stage, may not be easily corrected. An unfortunate, highly undesirable result of functional test failures that cannot be diagnosed and repaired is what is known in PCB/PCBA manufacturing as the “bone pile” of waste circuits.


Boundary-scan tools help mini- 1 3/3/15 11:46 AM


mize the bone-pile by assuring that no (or few) manufacturing defects escape to the functional testing stage. Using boundary-scan methods as a precursor to functional test reduces the amount of time needed to troubleshoot difficult-to-diagnose cir- cuit boards. Because of the precise diagnostic details provided by bound- ary-scan tools, circuit boards can be repaired with a single action rather than several procedures or actions. This precision will have a significant positive impact on product reliability and reduction of time-to-market.


The same tools used for bound-


ary-scan testing can also perform high-throughput, in-system program- ming (ISP) of flash memory devices, programmable logic devices (PLDs), and devices with embedded memory (such as microcontrollers). Programming is performed fol-


lowing board assembly at the optimal point in the manufacturing flow, and reprogramming can be performed eas- ily without having to remove devices from a PCB or PCBA. In addition to saving time, economic benefits result from reducing the number of tools,


Continued on next page


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