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March, 2015
Boundary-Scan Testing Checks Complex Circuit Designs
By Peter van den Eijnden, Managing Director, JTAG Technologies, Easton, MD
cations, has become the de facto stan- dard for testing complex digital and mixed-signal circuit designs during manufacturing of printed-circuit- board assemblies (PCBAs). While conventional test approaches such as in-circuit-test (ICT) methods may encounter difficulties due to lack of access to parts of a PCBA for probing circuit nodes, boundary-scan meth- ods succeed since they are treated as embedded test resources that are designed into the manufacturing of a PCBA from the start of the design and development of the product. The acceptance and adoption of
B
boundary-scan systems have grown and the level of automation of bound- ary-scan systems and their software have improved along with the quali- ty of models based on boundary-scan- description-language (BSDL) provid- ed by integrated-circuit (IC) suppli- ers. What may not be well known: there is a wide range of uses and working environments for boundary- scan systems and applications which, if considered “holistically,” can deliv- er benefits throughout a tested prod- uct’s life cycle and not just within the manufacturing test process.
Product Life Cycle As an electronic product moves
through its life cycle, from develop-
oundary-scan testing (also known as IEEE Standard 1149.1) and its related specifi-
ment stage through prototyping to manufacturing and finally to service and support phases, responsibility
from a variety of issues. Delays can result due to the use of different test methods and equip-
and resolved, such vital aspects as time-to-market, repair turnaround times, and product quality and relia- bility quickly escalate beyond accept- able limits. Symptoms of problematic transfers include extra design cycles, long prototype debug intervals, and logistical difficulties with prepro- grammed devices. For example, extra design cy -
cles, caused by poor test coordination and manufacturability, may involve multiple layout versions and proto- typing runs before a design is deemed ready for production. Long prototyping debug intervals can be caused in part by the presence of manufacturing faults that obscure design issues. Logistical difficulties with pre-
Manufacturing for test starts with designing JTAG ICs that become the gateway for truly effective testing.
for the product also migrates through the product’s manufacturing organi- zation. At the points of transfer from one department or discipline to the next within a company, significant delays and disruptions can occur
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programmed devices, such as wrong or out-of-date configurations of devices placed on PCBs for assembly, can result in assembly delays. Delays can stem from problems in manufac- turing fault clearing caused by poor test diagnostics and/or inaccurate documentation. In addition, delays can come from excessive time spent in troubleshooting PCBs and PCBAs, due to defective boards making it through structural testing. Delays can result from mystery failures in highly accelerated stress screen (HASS) or highly accelerated life testing (HALT) environmental test- ing, such as failures at a temperature
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