industry sapphire substrates
larger diameter substrates. According to analysis in 2012 by the US Department of Energy, 15 percent of the cost of the LED package is in the substrate, with the package accounting for a substantial fraction of the cost of the luminaire. If LED chipmakers migrate to larger diameter substrates, they will benefit from operational savings that more than offset the cost of the larger platforms. The lower-cost LEDs that result will then help to drive mass adoption of LED lighting for commercial and residential use.
Today, more than 90 percent of LEDs are built on sapphire, with the remainder on SiC, followed by other materials. To date, alternative substrates have failed to offer the performance and cost advantages of sapphire.
One platform that is attracting a lot of attention today is silicon. Proponents of this foundation are attracted to potential operational efficiencies that result from using 8-inch diameter wafers and the opportunity to use fully depreciated CMOS equipment. But these advantages must be weighed against the significant mismatches in the thermal expansion coefficients of silicon and GaN. Addressing this requires a costly, complex buffer layer to mitigate cracking and breakage. The manufacturing yields for GaN-on-silicon are reportedly still very low, while long-term reliability is unproven. So, until the technological hurdles are solved, silicon might be a niche solution, but is not expected to displace sapphire as the preferred substrate for LED production. Note that for cases where 8-inch diameters are important, we are capable of production volumes of 8-inch polished sapphire wafers.
Another frequently mentioned alternative to GaN-on- sapphire is GaN-on-GaN. However, 2-inch GaN substrates cost $1,000 or more, a hundred times the cost of sapphire. These high costs stem from a very complex fabrication process, and prevent a significant volume of this material from being available.
Given this backdrop, most LED chipmakers are looking to large diameter sapphire wafers to cut costs. Using this particular platform will enable more throughput in each run of the MOCVD reactor, making better use of the reactor ‘real estate’ and ultimately diminishing the cost per unit of area processed. In addition, large wafers reduce edge loss, and also provide post-MOCVD efficiencies.
Depending on the type of MOCVD reactor used, LED chip manufacturers using 6-inch wafer platforms can achieve up to 48 percent greater usable area, per reactor run, compared with 2-inch wafers. The overall surface area of a 6-inch wafer is
nine times that of a 2-inch wafer, and its outer curvature is less, enabling greater use of the surface area, culminating in a reduction in edge loss (see Figure 1). What’s more, when placed in an MOCVD reactor, there is greater coverage area in the reactor, resulting in further gains that are due to less waste of processing materials. Put all this together and all these efficiency gains associated with production on larger substrates become very compelling when LED chip production ramps up in large volumes to support a high growth market like general lighting.
Our substrates are also being consumed in a second significant market for sapphire – silicon-on- sapphire (SoS) RFICs. Sales of SoS RFIC chips are ramping up, because they combine high RF performance with low power consumption, a small form factor, and significantly reduced crosstalk in antenna applications that are pervasive in smart phones and other consumer devices. Sapphire is highly insulating, which helps the fabrication of devices that are fast, frugal, and offer high levels of isolation. In the last few years, SoS RFICs have gained a significant share of the smart phone antenna chip market, especially in the rapidly growing LTE networks, and they are now being marketed for other applications within these devices.
Vertical integration Vertical integration holds the key to our cost structure and the reliable supply of high-quality products. This integrated approach influences every step in the growth of sapphire crystals and their processing into wafers. Our end-to-end manufacturing capability, with strong intellectual property at each step of the manufacturing process, produces an advantageous cost structure and
March 2013
www.compoundsemiconductor.net 53
Figure 1: The proportion of chips that must be discarded due to ‘edge loss’diminishes as wafer sizes increase
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