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deposition  industry


Figure 7


Figure 10 Figure 8


between high and low (inner and outer radius) flux zones during deposition. Time averaging wafer residence between the zones offers uniform films without the need for masks. HULA fixtures demonstrated that wafers can be coated with high uniformity at effectively increased deposition rates without the need for masks. Figure 9 shows such a HULA fixture.


Conventional single-axis-of-rotation carriers fix wafers in inner and outer tier positions. Outer radius wafers get low deposition rates by virtue of location and single-axis-rotation. Inner radius wafers get rich flux and are coated faster. They therefore require selective masking reducing collection to match that of the outer tier wafer. In Figure 10, a mask is represented by the green triangle. Once installed, masks allow all wafers to be coated at the same


rate over a fixed number of carrier revolutions. Variations in different material/turret-pocket flux may be addressed by rate changes or through supplemental masks used to trim a select material/turret-pocket. Regardless of the mask employed, the maximum deposition rate in these systems is established by the deposition rates at the outer-tier position of the carrier for each material. The yellow arrow In Figure 11 indicates that this mask, optimized for gold uniformity resulted in a nominal 1000 Angstrom films.


By contrast, a HULA averages a wafer’s time spent in a range of flux zones by rotation and eliminates the need for the mask. This provides a normalized and effectively higher average deposition rate to all wafers on the carrier. It improves collection efficiency and uniformities of all different materials in a turret gun. Unmasked batch uniformities of <+/-3% for all turret-pockets from a source are regularly realized using the HULA. As Figure 12 shows, higher effective deposition rates (indicated by the yellow arrow) allow thickness set-points to be reached in shorter time. In many fabs, such an


Figure 9.HULA Substrate Carrier 32 www.compoundsemiconductor.net March 2013 Figure 11


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