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www.us-tech.com
September, 2017
Ambient Shadow Moiré Warpage Measurements Reduce Defect Rates
By Eric Moen, Vice President of Sales and Marketing, Akrometrix T
he electronics assembly indus- try is being challenged with materials, components and assemblies that are more prone to warpage-induced defects both pre- reflow and in-between reflow stages. The majority of traditional warpage and deformation testing has taken place in a controlled environment. During testing, shadow moiré or some other method of metrology, recommended by standards such as JEDEC JESD22-B112A and JEITA ED-7306, is performed in a thermal environment designed to emulate the reflow oven. However, there is an in- creasing interest in measuring the flatness of substrates, compo- nents and materials at ambient temperature in the assembly area. Components and substrates are getting smaller, thinner, and are adding layers of complexity, which all affect their coefficients of thermal expansion (CTE) and the resulting warpage.
A Study in Warpage
A recent study was conducted to identify the key factors contributing to the warpage of a particular mod- ule, soldered directly to a carrier board using a land grid array (LGA) pattern. This type of solder joint is relatively thin — defined only by the thickness of the deposited solder paste — and therefore highly sensi- tive to warpage effects. The manufac- turer was experiencing high failure rates due to open solder joints at the
corners of the module.
Incoming module arrays were initially hand-sorted using IPC-TM- 650 Test Method 2.4.22 into three categories, according to their severity of warpage. This process of hand- sorting boards was arduous, leading the team to look for a more efficient method. The manufacturer was able
cuits in a short period of time. The results of the study were published in a paper, “Understand- ing PCB Design Variables that Contribute to Warpage During Module-Carrier Attachment,” which was presented at SMTA Inter- national in 2016.
The initial rough measure-
bare PCBs, many of which were des- tined to be scrapped. When data was being collected for the study, the only available method for shadow moiré measurement of room temperature samples was to place each six-up sample into a warpage measurement tool that contained an oven chamber at room temperature, capture the warpage data, remove, and repeat.
With the introduction of Akrometrix’s TTSM (tabletop shadow moiré) system, users now have access to a low-cost tool that more effectively gathers warpage data without the complexity of an oven chamber.
Samples and Results
49 mm (1.9 in.) module (left) and a full 132 mm (5.2 in.) six-up module pallet.
to reduce its defects per million (DPM) from 50,000 to 10,000. This was an obvious improvement, but still well above the company’s target defect rate of 1,500.
In phase two of the study, the DPM rate was reduced to the target of 1,500 after identifying the two pri- mary causes of the warpage defects. The key to this success was using shadow moiré, which allowed the team to analyze large numbers of cir-
ments were enough to pinpoint warpage as the cause of the high fail- ure rate. But, they did not offer full warpage data on the modules, and did not allow data to be tracked or stored for each individual module. Shadow moiré was used to measure the boards much more accurately, fine-tuning the study.
The company measured a sta- tistically-relevant sample of its six- up daughter cards, more than 6,500
The module/daughterboard seemed to be causing the prob- lems, not the carrier. IPC 610 warpage guidelines for the bow and twist of boards allow 0.7 mm (0.03 in.) on each module and 2.0 mm (0.08 in.) on the six-up panel. But, a unique “pad-only” surface on the interconnect side of the company’s module only allowed for a seating plane of less than 0.18 mm (0.007 in.) on the module and less than 0.5 mm (0.02 in.) on the six-up pallet. This is only 25 percent of the generally accepted warpage for stan- dard BGAs and SMT devices. The probability of failure was found to increase significantly — greater than a 1.08 percent failure rate — once the coplanarity of the module exceeded the seating plane of 0.18 mm (0.007 in.).
If the LGA experienced war- page, then it was likely that the sol- der paste would not make proper contact with the LGA at its liquidus temperature, resulting in non-con- tact or cold solder defects.
See at SMTAI, Booth 115
The data confirmed this hypoth- esis. The team separated the total 6,684 modules into three groups. Group A was the acceptable group, in which warpage was less than the 0.5 mm (0.02 in.) seating plane. Group B, the moderate group, experienced warpage between 0.5 and 1 mm (0.02 and 0.04 in.). Group C was labeled severe and its warpage was anything greater than 1 mm (0.04 in.). Initial measurements were made by feeler gauge, but the final DOE measurements, at room tem- perature in between each reflow cycle, were measured with shadow moiré. All 6,684 modules (1,114 six- up panels) were then assembled, so that a ppm failure rate could be determined per category. Group A (2,760 measured samples) saw a fail- ure rate of only 513 ppm. This sharply contrasts with Group B (2,760 samples), which had a failure rate of 28,751 ppm. Group C (1,164 samples) was even more extreme, with a failure rate of 50,301 ppm. Ultimately, the team found that by improving the stiffness of the
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