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Conference report  IEDM


However, it is challenging to form high-quality III-V layers on silicon, due to a significant difference in lattice mismatch and a fundamental difference in polarity between the substrate and epilayers.


To address this several research teams have learnt how to grow III-V buffer layers on either blanket or patterned silicon wafers. These efforts have been performed primarily by MBE, which offers excellent process control. However, this deposition technique is line-of- sight and non-selective, characteristics that pose challenges for process integration and conformal growth on non-polar, three-dimensional devices. MOCVD is a more promising growth technology for making III-V transistors on silicon, thanks to its strengths of selective area growth and deposition on three- dimensional structures. There have been very few efforts in this direction, but at IEDM 2011 a partnership between Intel and IQE claimed to report the first direct comparison between III-V-on-silicon transistors grown by these two rival deposition techniques. Their conclusions: The material quality of the epilayers deposited by MOCVD is comparable to the best films grown by MBE, and the Hall mobility in the channel of the MOCVD-grown III-V-on-silicon transistor at room- temperature is as good as that of the ‘gold-standard’ – an MBE-grown, III-V transistor formed on InP.


dielectrics deposited by atomic layer deposition revealed that MBE and MOCVD can form InP layers with a low mid-gap density of interface states. The team’s next step was to produce In0.7


Researchers from Intel and IQE began by comparing the performance of InP films deposited on native substrates by MBE and MOCVD. Multi-frequency capacitance-voltage curves using TiN metal gates and TaSiOx


Ga0.3 As QW FETs with a


high-k dielectric on InP. Again, MOCVD-grown devices were the equal of those made by MBE: Both transistors delivered similar values for sub-threshold swing and produced comparable plots of ‘on-current’ as a function of ‘off-current’.


Figure 6. At imec researchers have developed GaN double- heterostructure FETs that feature a silicon trench around the gate.This unique feature improves the buffer leakage current by up to three orders of magnitude


To compare the two deposition techniques for growth of III-V QW FETs on silicon, the researchers selected 75 mm


(100) silicon substrates with a 4° off-cut. According to them, they employed the thinnest buffer ever reported: 0.5 µm of GaAs, followed by a 0.7 µm-thick graded layer of Inx


Al1-xAs and a 0.1 µm-thick In0.53 Ga0.47


As bottom


barrier. The graded ternary features an overshoot of indium concentration to x=0.7, before the composition is brought back to end at x=0.52. Doing this ensures full relaxation in the buffer and means that the bottom barrier is lattice-matched to a 50 nm-thick, In0.53


Ga0.47 As QW.


Atomic force microscopy (AFM) reveals that the GaAs buffer grown by MOCVD is slightly smoother than its MBE-grown cousin. Its material quality is also better, according to X-ray diffraction. And scrutinizing the interface of silicon and GaAs with cross-sectional TEM reveals yet another advantage of MOCVD: Defects are confined at the interface, rather than spreading through the layer.


These characterization techniques have also been used to assess the quality of full epitaxial structures. AFM measurements reveal that the MBE-grown sample is slightly smoother than its MOCVD-based rival, and X-ray diffraction measurements indicate that the material quality of the In0.53


Ga0.47 As bottom barrier and quantum


well are very similar in both samples. Inspection with the TEM indicates a complete lack of defects in the samples grown on InP, and a defect density of 2 x 109


cm-2 in


both silicon-based samples, which had defects typically 50 nm by 100 nm in size. Hall measurements reveal very promising values for the carrier mobilities of the MBE-grown III-V FETs on silicon. At 300 K, mobility was typically 8000 cm2 cm2


V-1 V-1 s-1 .


GaN FETs with thinner buffers An entirely different class of III-V-on-silicon transistors were discussed in a paper by Puneet Srivastava from imec: GaN double-heterostructure FETs featuring a Silicon Trench Around the Drain (STAD) contact. The merit of this novel device is the combination of a 2 kV breakdown voltage and good performance at elevated temperature, despite the use of a relatively thin buffer.


With conventional GaN-on-silicon HEMTs, the high breakdown voltage stems from a thick buffer layer – typically 7 µm to realise a 2 kV blocking voltage. If the buffer is much thinner than this, the transistor prematurely fails through interfacial conduction across the AlGaN-silicon interface. Thick buffer layers prevent this but present their own problems, such as strain in the epiwafers that can lead to bowing of the wafer and even crack formation. Previously, imec’s researchers had managed to realise high breakdown voltages with buffers just 2 µm-thick by removing a small region of the silicon substrate between the source and drain contacts.


“With this technique, we achieved a high breakdown voltage of over 2 kV,” says Srivastava. “But the devices suffered from enhanced self-heating, because there is


18 www.compoundsemiconductor.net January/February 2012 s-1 , and at 77 K it exceeds 22,000


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