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Conference report  IEDM


to address this issue. These three-dimensional devices enshroud the channel with a dielectric to control current flow. “It’s the same story happening with III-Vs, because the device physics is, in principle, the same,” says Ye. His student, Jiangjiang Gu, took two years to figure out how to make a gate-all-around III-V MOSFET. He focused on finding a simple approach to making this device that would employ processes suitable for use in a silicon foundry.


Device fabrication begins with MBE growth of a 30 nm- thick InGaAs layer on p-doped InP. Implanting silicon ions creates source and drain regions, and a lithographic process forms nanowire InGaAs channels (see Figure 1).


Figure 2.(a) An SEM image of the InGaAs nanowire test structures after the release process (b) Cross-sectional TEM of the InGaAs nanowires wrapped in the dielectric (c) A finished InGaAs gate- all-around FET with 4 fingers


make a three-dimensional III-V transistor: Many other research groups have already achieved that feat, but in every case they have formed nanowire structures with a ‘bottom-up’ approach.


“Industry has interest in that work, but not strong interest,” explains Peide Ye, leader of III-V MOSFET research at Purdue University. He points out that bottom-up techniques tend to produce wires that have a random arrangement. “It is difficult to put these transistors where you want, and connect them together to form a circuit.”


According to Ye, the silicon industry is far more interested in developments involving top-down approaches. That includes the lithography, dry/wet etching and atomic layer deposition (ALD) processes that he and his co-workers have used to fabricate their MOSFET. Three-dimensional transistors benefit from wrapping of the dielectric around the channel to minimize so-called ‘short-channel effects’. In general, these are exacerbated as the transistor’s feature sizes are scaled down, because miniaturization must include a thinning of the dielectric used for making the gate.


When the silicon industry reached the 45 nm node it departed from the traditional silicon dioxide gate, using hafnium dioxide instead to temper short-channel effects. At the 22 nm node these effects are even more severe, so chipmakers are turning to three-dimensional transistors


Anisotropic wet etching with hydrochloric acid removes InP, including that beneath the InGaAs channel. This is only successful when the channel is aligned along the [010] direction, an orientation that produces undercut etching.


ALD, which is a ‘super-conformal’ process, wraps the channel in a 10 nm-thick coating of Al2


O3 and then


surrounds it with a WN gate. A second lithographic step selectively removes part of the WN layer, allowing contacts to be made to the source and drain regions.


The MOSFETs that result have been produced with either one, four, nine or 19 InGaAs nanowire channels (see Figure 2). Using multiple wires allows the researchers to not only study their uniformity, but also increase total current delivery.


High values for transconductance and drain current showcase the promise of these devices for forming high-speed logic circuits. Devices with a 50 nm gate length have a transconductance of 710 µS/µm, revealing that scaling to small dimensions is not detrimental to transistor performance (see Figure 3). “With our planar devices, after 150 nm you are out of control,” says Ye.


Drain current, which has been normalized by the perimeter of the wire to allow fair comparison with results for planar structures, peaks at 1.17 mA/mm for a ‘hero’ device. “That’s a very high current – higher than the III-V bottom-up work.”


Figure 3. The gate-all- around FETs set a new benchmark for transconduct- ance at short gate lengths, indicating their potential for making high- speed logic circuits


16 www.compoundsemiconductor.net January/February 2012


Typical values for sub-threshold swing and drain- induced barrier lowering for a device with a 50 nm gate length are 150 mV/dec and 210 mV/V, respectively. These values are too high, and Ye admits that progress is needed: “The interface is difficult and there is still a lot of engineering work to be done. The sub-threshold slope needs to come down to 65-70.”


Reducing the power Another advantage of III-Vs over silicon is their greater potential to reduce the power density in logic circuits. III-Vs promise to work at lower operating voltages, which must be introduced as feature sizes are scaled to prevent a dramatic increase in the power density within


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