TECHNOLOGY SiC POWER ELECTRONICS
Figure 5. Forward characteristics for a 1 kV SiC SBD, a 20 kV SiC SBD, and a 20 kV SiC pin diode with two different carrier lifetimes (simulated). For 20 kV applications, a pin diode with sufficiently long carrier lifetime is the most promising
Figure 6. Eliminating defects increases the carrier lifetime in SiC. Lifetimes are revealed by microwave-detected photoconductance decay measurements, which show the improvement in a 220 μm-thick epilayer that results from the defect-elimination process
ultra-high-voltage SiC device. To prevent this from impacting device performance, the structure and the doping profile of the Al+
-implanted junction-
termination-extension (JTE) region have to be carefully designed and optimised. If the aluminium doping concentration is too low, severe electric field crowding occurs near the mesa edge; but if this doping is too high, crowding is present at the outer edge of the JTE region.
We address this issue with a ‘space-modulated’ JTE structure featuring multiple rings formed inside a reduced surface field-type, Al+
JTE region. By modulating the widths and spacing of individual rings, the effective JTE dose gradually decreases as it progresses toward the outer edge. In turn, this minimises electric field crowding and provides a wide optimum JTE dose range. Device simulations enabled optimisation of the structure and the doping profile of the JTE region (see Figure 8).
Our most recent pin diodes have a 260 μm-thick voltage-blocking layer. Mesa diameter and the JTE
-implanted
length are just 300 μm and 1050 μm, respectively – that’s because the aim of producing this diode is
to provide a proof of the concept and not a power device capable of handling very high currents.
Device testing involved immersion of the diode in the dielectric liquid Fluorinert, and on-wafer testing with a DC voltage sweep (see Figure 9). Determining device performance is not easy, because no suitable commercial UHV testing systems are available at present, and we had to address several technical issues related to cable connections and the probe configuration to prevent air sparking.
Our devices can withstand voltages up to 26.9 kV (see Figure 10), the limit of our measurement set-up, and they set a new benchmark for any solid-state device. We estimate that the real breakdown voltage is more than 30 kV, but we will only be able to prove this after improving our measurement system. On-resistance of this diode is just 19 mΩ cm2
, compared with 430 mΩ cm2
Figure 7. Fabrication of the SiC pin diode involved epitaxial growth of a very thick n-type voltage-blocking layer and a highly-doped p-type emitter, followed by diode isolation that resulted from formation of an improved bevel mesa with a rounded bottom. This alleviates electric field crowding near the junction edge
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www.compoundsemiconductor.net March 2014
for a SBD (no carrier injection) processed on the same wafer without a p-type anode. This pair of results underlines how the conductivity modulation effect can slash the resistance of a very thick, lightly-doped layer. The original carrier-lifetime enhancement technique has helped to realise a low on-resistance in our devices. Analysing the resistance components with our
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