TECHNOLOGY SiC POWER ELECTRONICS
option at lower blocking voltages, such as 1 kV, because in this regime it exhibits very good on- state characteristics. However, when the voltage requirement increases to 20 kV, the on-resistance climbs to unacceptable levels (see Figure 5). So, at these ultra-high voltages, the SiC pin diode is a better choice, thanks to the long lifetime of its injected carriers. This long lifetime is due to the indirect band gap and high crystalline quality, and is a key factor for attaining the conductivity modulation effect.
However, a long carrier lifetime is not guaranteed in a SiC device. Back in 2007 we identified a carrier-lifetime killer in this wide bandgap material − a deep level, known as a Z1/2
centre, that is
located 0.62 eV below the conduction band. But by 2009 we had succeeded in eliminating this defect, an acceptor level of a single carbon vacancy, by thermal oxidation.
This thermal oxidation process leads to the formation of SiO2
on the surface of SiC. But what
happens to the carbon? That’s a long-standing and still-open question, but in our view most carbon atoms diffuse out as a form of CO, while a smaller number remain near the SiO2
/SiC
interface. Here they can even be emitted into the SiC side, where they will diffuse in the bulk region. Carbon vacancies here are filled with diffusing carbon interstitials, ensuring that the lifetime killer is eliminated from the surface right down to deep in the epilayers.
Armed with this this innovative defect-elimination
technique, we realised a lifetime of over 30 μs (see Figure 6). Surface recombination is now the barrier to longer lifetimes, which should be in
excess of 50 μs. But even with our current values for carrier lifetime, we can realise conductivity modulation of 20 kV devices.
To ultra-high voltages Fabrication of 20 kV SiC devices requires the growth of a voltage-blocking layer at least 150 μm-thick and doped to a carrier concentration of no more than low ~1014
cm−3 . Such a film can be grown homoepitaxially by CVD at 1650°C on
Figure 3. Electric field distributions in one-sided abrupt junction in SiC and silicon are markedly different, even though they have the same breakdown voltages. That’s because: the breakdown field strength for SiC is ten times that for silicon, so the thicknesses of the voltage-blocking layers of SiC power devices can be one-tenth of that in the corresponding silicon devices; and the doping concentration in the SiC devices can be two orders of magnitude higher than that in the silicon counterparts
low-resistivity n-type SiC (0001) substrates. Fast growth rates are very attractive for such a thick layer. In our group, we have successfully
increased the SiC growth rate from 10 μm/h to beyond 50 μm/h. This has been accomplished while avoiding issues related to nitrogen donor
contamination, by either reducing the growth pressure or increasing the ratio of carbon-to- silicon in the precursor gases. These refinements enable background doping concentrations in the SiC epitaxial layers of less than 1×1013
cm−3
which is sufficiently low for the development of ultra-high voltage devices.
Fabrication of our SiC pin diode involved epitaxial growth of an n-type, very thick voltage-blocking layer, and a highly doped p-type emitter that acts as an anode. Diode isolation followed, using an improved bevel mesa structure with a rounded bottom. To alleviate electric field crowding near the junction edge − which causes the device to breakdown at a much lower voltage than what should be expected from calculations based on thickness and doping concentration − we then employed an Al+
implantation process and
subsequent activation annealing to create an appropriate junction termination structure (see Figure 7). After this, we added ohmic contacts for the p-type anode and the n-type cathode from Al/Ti layers and a nickel layer sintered at 1000 °C. Thermal oxidation and deposition of a
4 μm-thick polyimide film passivated the surface and prevented surface arcing. Note that fabrication also involved a thermal oxidation-based lifetime enhancement process, performed after the epitaxial growth of the n-type voltage-blocking layer.
Figure 4. The last decade has witnessed a significant increase in blocking voltages of SiC pin diodes
Alleviating electric field crowding is one of the greatest challenges associated with forming an
March 2014
www.compoundsemiconductor.net 55 ,
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84 |
Page 85 |
Page 86 |
Page 87 |
Page 88 |
Page 89 |
Page 90 |
Page 91 |
Page 92 |
Page 93 |
Page 94 |
Page 95 |
Page 96 |
Page 97 |
Page 98 |
Page 99 |
Page 100 |
Page 101 |
Page 102 |
Page 103 |
Page 104 |
Page 105 |
Page 106 |
Page 107 |
Page 108 |
Page 109 |
Page 110 |
Page 111 |
Page 112 |
Page 113 |
Page 114 |
Page 115 |
Page 116 |
Page 117 |
Page 118 |
Page 119 |
Page 120 |
Page 121 |
Page 122 |
Page 123 |
Page 124 |
Page 125 |
Page 126 |
Page 127 |
Page 128 |
Page 129 |
Page 130 |
Page 131 |
Page 132 |
Page 133 |
Page 134 |
Page 135 |
Page 136 |
Page 137 |
Page 138 |
Page 139 |
Page 140 |
Page 141 |
Page 142 |
Page 143 |
Page 144 |
Page 145 |
Page 146 |
Page 147 |
Page 148 |
Page 149 |
Page 150 |
Page 151 |
Page 152 |
Page 153 |
Page 154 |
Page 155 |
Page 156 |
Page 157 |
Page 158 |
Page 159 |
Page 160 |
Page 161 |
Page 162 |
Page 163 |
Page 164