technology transistor architectures
Figure
1.Three different device structures designed for high speeds and fabricated under the sponsorship of the DARPA NEXT program: a state-of-the-art InAlN/GaN transistor fabricated by Tomas Palacios and co- workers at MIT (a); an N-face transistor fabricated at UCSB (b) an AlN/GaN high-speed transistor from HRL (c)
Radical requirements
One of the biggest obstacles facing engineers wanting to fabricate devices operating at unprecedented speeds, such as of 500 GHz or more, is that they cannot work with conventional nitride transistors that employ the pairing of GaN and AlGaN. Conventional transistor structures require AlGaN barriers with a thickness in excess of 20 nm to induce a high enough carrier density in the channel. This thickness has a major downside for high speeds: It leads to a relatively large distance between the gate metal and the channel, and ultimately reduces the ability of the gate electrode to efficiently modulate the channel electrons. Gate recesses have been proposed to mitigate this problem, but the the damage introduced by the gate recess introduces new challenges.
The good news is that there are three alternative architectures that promise to yield transistors operating at ultra-high frequencies: InAlN/GaN heterostructures, which are being investigated by several research teams, including our group at Massachusetts Institute of Technology; nitrogen-face GaN/AlGaN devices; and AlN/GaN structures. In all three cases, researchers are reaching higher and higher speeds through aggressive scaling of the dimensions of the transistor in both lateral and vertical directions.
Such efforts are aided by DARPA, which is funding the Nitride Electronic NeXT Generation Technology (NEXT) programme. US agencies have a good track record in helping to advance GaN technology, and through The Office of Naval Research it previously funded the Millimeter-wave Initiative in Nitride Electronics, Multi- University Research Initiative (MINE MURI). Of these three nascent technologies, arguably the most established is the InAlN/GaN heterostructure, which was first proposed by Jan Kuzmik from the Slovak Academy
34
www.compoundsemiconductor.net August / September 2011
of Science in 2001.
Transistors made with InAlN and GaN can realize extremely high charge densities, due to the large polarization discontinuity between the InAlN barrier and the GaN channel. However, the benefits of polarization discontinuity are not limited to a reduction in the access resistance of these devices – this architecture also suppresses short-channel effects in deep-submicron transistors. It is also worth noting that this suppression does not require the use of a gate recess process that can introduce plasma damage during the dry etching step.
By taking advantage of these strengths, several groups have been able to attain outstanding results for short- channel InAlN/GaN transistors. Last year a Swiss partnership between ETH-Zurich and EPFL reported a 100-nm gate length InAlN/GaN transistor with a cut-off frequency (fT frequency (fMAX
to trump that effort and hit an fT of 205 / 191 GHz
) of 144 GHz, and a maximum oscillation ) of 137 GHz. It did not take long for them / fMAX
with a 55-nm gate-length device. More recently, we have set a new benchmark for InAlN/GaN transistors, working in close collaboration with the University of Notre Dame and the companies TriQuint and IQE. Our 30 nm gate length device produces an fT
of 300 GHz, the highest cut-off frequency ever reported for GaN transistors (see Figure 1).
Fabrication of this record-breaking device stemmed from a combination of gate-length scaling and the introduction of novel technologies that were able to squeeze a few more gigahertz from this transistor. These technologies included vertical scaling of the device, which holds the key to reduced short channel effects, and also led to an increase in the modulation efficiency of the gate electrode and higher frequency performance.
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